component
PESD15VS2UT-N
Public Made by Adomby adom
BORN ESD And Surge Protection (TVS/ESD), SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| pesd15vs2ut-n-etched.glb | 8d ago |
| pesd15vs2ut-n-etched.step | 8d ago |
| pesd15vs2ut-n-hero.glb | 8d ago |
| pesd15vs2ut-n-hero.overlay.json | 8d ago |
| pesd15vs2ut-n.glb | 8d ago |
| pesd15vs2ut-n.kicad_mod | 8d ago |
| pesd15vs2ut-n.kicad_sym | 8d ago |
| pesd15vs2ut-n.lbr | 8d ago |
| pesd15vs2ut-n.step | 8d ago |
| README.md | 8d ago |
PESD15VS2UT-N
BORN · ESD And Surge Protection (TVS/ESD) · SOT-23
PESD15VS2UT-N from BORN, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1 | passive | One of the two protected line pins of the bidirectional ESD protection diode array, with junction capacitance of 50 to 55 pF to pin 3 at VR = 0 V and 1 MHz. |
| 2 | 2 | passive | The other protected line pin of the ESD protection diode array, with junction capacitance of 50 to 55 pF to pin 3 at VR = 0 V and 1 MHz. |
| 3 | 3 | passive | Common pin of the diode array, referenced by the datasheet as the second terminal for the pin 1 and pin 2 junction capacitance; the datasheet does not name it as ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BORN |
| Package | SOT-23 |
| Category | Circuit Protection |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse Breakdown Voltage | VBR | 16.7 | 17.6 | 20 | V | IT=1mA | 2 |
| Reverse Leakage Current | IR | 0.1 | 0.5 | μA | VRWM=15V,T=25℃ | 2 | |
| Junction Capacitance | Cj | 50 | 55 | pF | VR = 0V, f = 1MHz (Pin1、Pin2 to Pin 3) | 2 | |
| Reverse Stand-Off Voltage | VRWM | 15 | V | 2 | |||
| Peak Pulse Current | IPP | 10 | A | tp =8/20μs | 2 | ||
| Clamping Voltage | VC | 35 | V | IPP=10A,tp=8/20μs | 2 | ||
| Peak Pulse Power | PPP | 350 | Watts | tp =8/20μs | 2 | ||
| Peak Pulse Current | Ipp | 10 | A | tp =8/20μs (note1) | 2 | ||
| ESD per IEC 61000-4-2 (Air) | VESD | 30 | kV | IEC 61000-4-2 (Air) | 2 | ||
| ESD per IEC 61000-4-2 (Contact) | VESD | 30 | kV | IEC 61000-4-2 (Contact) | 2 | ||
| Lead Soldering Temperature | TL | 260 | ℃ | 10 seconds | 2 | ||
| Junction Temperature | TJ | -55 | 125 | ℃ | 2 | ||
| Storage Temperature | Tstg | -55 | 125 | ℃ | 2 |
CAD (KiCad official)
- Symbol:
PESD15VS2UT-N - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
pesd15vs2ut-n-etched.step/pesd15vs2ut-n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pesd15vs2ut-n.step/pesd15vs2ut-n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: BORN datasheet (4 pp, sha256
14796aa97b89c9dd, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).