component

PESD15VL2BT-N

Public Made by Adom

by adom

BORN ESD And Surge Protection (TVS/ESD), SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PESD15VL2BT-N

BORN · ESD And Surge Protection (TVS/ESD) · SOT-23

PESD15VL2BT-N from BORN, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1 passive One of the two protected data-line pins; junction capacitance to Pin 3 is 20 pF typical and 25 pF maximum at VR = 0 V, f = 1 MHz.
2 2 passive The second protected data-line pin; junction capacitance to Pin 3 is 20 pF typical and 25 pF maximum at VR = 0 V, f = 1 MHz.
3 3 passive Common pin referenced by the Pin 1 and Pin 2 junction capacitance test condition; the datasheet does not name its function explicitly, and the device has a 15 V reverse stand-off voltage (VRWM) across the protected line pins.

Key specifications

Parameter Value
Manufacturer BORN
Package SOT-23
Category Circuit Protection
Pins 3

CAD (KiCad official)

  • Symbol: PESD15VL2BT-N
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pesd15vl2bt-n-etched.step / pesd15vl2bt-n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pesd15vl2bt-n.step / pesd15vl2bt-n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BORN datasheet (4 pp, sha256 9297a731d42eeb34, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF