component
PEMD2
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Nexperia Digital Transistors, SOT-666. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PEMD2
Nexperia · Digital Transistors · SOT-666
PEMD2 from Nexperia, in a SOT-666. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND (emitter) TR1 | power_in | Emitter of the built-in NPN transistor TR1 and the ground reference for TR1; the datasheet lists it as GND (emitter) TR1 in Table 3. |
| 2 | input (base) TR1 | input | Base input of TR1 through the built-in 22 kΩ bias resistor R1; TR1 input voltage limits are +40 V positive and −10 V negative per Table 6. |
| 3 | output (collector) TR2 | output | Collector output of the PNP transistor TR2, with output current limited to 100 mA per Table 6. |
| 4 | GND (emitter) TR2 | power_in | Emitter of the built-in PNP transistor TR2 and the ground reference for TR2, as listed in Table 3. |
| 5 | input (base) TR2 | input | Base input of TR2 through the built-in 22 kΩ bias resistor R1; TR2 input voltage limits are given in Table 6. |
| 6 | output (collector) TR1 | output | Collector output of the NPN transistor TR1, with output current limited to 100 mA per Table 6. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-666 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO | 50 | V | open emitter | 4 | ||
| collector-emitter voltage | VCEO | 50 | V | open base | 4 | ||
| emitter-base voltage | VEBO | 10 | V | open collector | 4 | ||
| input voltage TR1 positive | VI | 40 | V | 4 | |||
| input voltage TR1 negative | VI | 10 | V | 4 | |||
| input voltage TR2 positive | VI | 10 | V | 4 | |||
| input voltage TR2 negative | VI | 40 | V | 4 | |||
| output current | IO | 100 | mA | 4 | |||
| peak collector current | ICM | 100 | mA | single pulse; tp ≤ 1 ms | 4 | ||
| total power dissipation per transistor (SOT666) | Ptot | 200 | mW | Tamb ≤ 25 °C; FR4 PCB, standard footprint | 4 | ||
| total power dissipation per device (SOT666) | Ptot | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, standard footprint | 4 | ||
| junction temperature | Tj | 150 | °C | 4 | |||
| ambient temperature | Tamb | -55 | 150 | °C | 4 | ||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| thermal resistance from junction to ambient, per transistor (SOT666) | Rth(j-a) | 625 | K/W | in free air; FR4 PCB, standard footprint | 5 | ||
| thermal resistance from junction to ambient, per device (SOT666) | Rth(j-a) | 417 | K/W | in free air; FR4 PCB, standard footprint | 5 | ||
| collector-base cut-off current | ICBO | 100 | nA | VCB = 50 V; IE = 0 A | 8 | ||
| collector-emitter cut-off current | ICEO | 100 | nA | VCE = 30 V; IB = 0 A | 8 | ||
| collector-emitter cut-off current at Tj = 150 °C | ICEO | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 8 | ||
| emitter-base cut-off current | IEBO | 180 | µA | VEB = 5 V; IC = 0 A | 8 | ||
| DC current gain | hFE | 60 | VCE = 5 V; IC = 5 mA | 8 | |||
| collector-emitter saturation voltage | VCEsat | 150 | mV | IC = 10 mA; IB = 0.5 mA | 8 | ||
| off-state input voltage | VI(off) | 1.1 | 0.8 | V | VCE = 5 V; IC = 100 µA | 8 | |
| on-state input voltage | VI(on) | 2.5 | 1.7 | V | VCE = 0.3 V; IC = 5 mA | 8 | |
| bias resistor 1 (input) | R1 | 15.4 | 22 | 28.6 | k | 8 | |
| bias resistor ratio R2/R1 | R2/R1 | 0.8 | 1 | 1.2 | 8 | ||
| collector capacitance TR1 (NPN) | Cc | 2.5 | pF | VCB = 10 V; IE = ie = 0 A; f = 1 MHz | 8 | ||
| collector capacitance TR2 (PNP) | Cc | 3 | pF | VCB = 10 V; IE = ie = 0 A; f = 1 MHz | 8 |
CAD (KiCad official)
- Symbol:
PEMD2 - Footprint:
Package_TO_SOT_SMD:SOT-666 - 3D model: SOT-666 (KiCad packages3D, STEP)
- 3D model files:
pemd2-etched.step/pemd2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pemd2.step/pemd2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
3f5f9312c616942d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PEMD2
**Nexperia** · Digital Transistors · SOT-666
PEMD2 from Nexperia, in a SOT-666. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND (emitter) TR1 | power_in | Emitter of the built-in NPN transistor TR1 and the ground reference for TR1; the datasheet lists it as GND (emitter) TR1 in Table 3. |
| 2 | input (base) TR1 | input | Base input of TR1 through the built-in 22 kΩ bias resistor R1; TR1 input voltage limits are +40 V positive and −10 V negative per Table 6. |
| 3 | output (collector) TR2 | output | Collector output of the PNP transistor TR2, with output current limited to 100 mA per Table 6. |
| 4 | GND (emitter) TR2 | power_in | Emitter of the built-in PNP transistor TR2 and the ground reference for TR2, as listed in Table 3. |
| 5 | input (base) TR2 | input | Base input of TR2 through the built-in 22 kΩ bias resistor R1; TR2 input voltage limits are given in Table 6. |
| 6 | output (collector) TR1 | output | Collector output of the NPN transistor TR1, with output current limited to 100 mA per Table 6. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-666 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO | | | 50 | V | open emitter | 4 |
| collector-emitter voltage | VCEO | | | 50 | V | open base | 4 |
| emitter-base voltage | VEBO | | | 10 | V | open collector | 4 |
| input voltage TR1 positive | VI | | | 40 | V | | 4 |
| input voltage TR1 negative | VI | | | 10 | V | | 4 |
| input voltage TR2 positive | VI | | | 10 | V | | 4 |
| input voltage TR2 negative | VI | | | 40 | V | | 4 |
| output current | IO | | | 100 | mA | | 4 |
| peak collector current | ICM | | | 100 | mA | single pulse; tp ≤ 1 ms | 4 |
| total power dissipation per transistor (SOT666) | Ptot | | | 200 | mW | Tamb ≤ 25 °C; FR4 PCB, standard footprint | 4 |
| total power dissipation per device (SOT666) | Ptot | | | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, standard footprint | 4 |
| junction temperature | Tj | | | 150 | °C | | 4 |
| ambient temperature | Tamb | -55 | | 150 | °C | | 4 |
| storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| thermal resistance from junction to ambient, per transistor (SOT666) | Rth(j-a) | | | 625 | K/W | in free air; FR4 PCB, standard footprint | 5 |
| thermal resistance from junction to ambient, per device (SOT666) | Rth(j-a) | | | 417 | K/W | in free air; FR4 PCB, standard footprint | 5 |
| collector-base cut-off current | ICBO | | | 100 | nA | VCB = 50 V; IE = 0 A | 8 |
| collector-emitter cut-off current | ICEO | | | 100 | nA | VCE = 30 V; IB = 0 A | 8 |
| collector-emitter cut-off current at Tj = 150 °C | ICEO | | | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 8 |
| emitter-base cut-off current | IEBO | | | 180 | µA | VEB = 5 V; IC = 0 A | 8 |
| DC current gain | hFE | 60 | | | | VCE = 5 V; IC = 5 mA | 8 |
| collector-emitter saturation voltage | VCEsat | | | 150 | mV | IC = 10 mA; IB = 0.5 mA | 8 |
| off-state input voltage | VI(off) | | 1.1 | 0.8 | V | VCE = 5 V; IC = 100 µA | 8 |
| on-state input voltage | VI(on) | 2.5 | 1.7 | | V | VCE = 0.3 V; IC = 5 mA | 8 |
| bias resistor 1 (input) | R1 | 15.4 | 22 | 28.6 | k | | 8 |
| bias resistor ratio R2/R1 | R2/R1 | 0.8 | 1 | 1.2 | | | 8 |
| collector capacitance TR1 (NPN) | Cc | | | 2.5 | pF | VCB = 10 V; IE = ie = 0 A; f = 1 MHz | 8 |
| collector capacitance TR2 (PNP) | Cc | | | 3 | pF | VCB = 10 V; IE = ie = 0 A; f = 1 MHz | 8 |
## CAD (KiCad official)
- Symbol: `PEMD2`
- Footprint: `Package_TO_SOT_SMD:SOT-666`
- 3D model: SOT-666 (KiCad packages3D, STEP)
- 3D model files: `pemd2-etched.step` / `pemd2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pemd2.step` / `pemd2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913725110177792) (19 pp, sha256 `3f5f9312c616942d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pemd2-datasheet.pdf)