component
PDTD123EUX
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-323-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPDTD123EUX
Nexperia · Digital Transistors · SOT-323-3
PDTD123EUX from Nexperia, in a SOT-323-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | input (base) | input | Input (base) of the built-in NPN transistor, tied to bias resistor R1 (2.2 kΩ typical for PDTD123EU), with input voltage VI limited to −10 V to +12 V for PDTD123EU. |
| 2 | GND (emitter) | power_in | Ground/emitter of the built-in NPN transistor, with emitter-base voltage VEBO limited to 10 V maximum for PDTD123EU. |
| 3 | output (collector) | output | Output (collector) of the built-in NPN transistor, rated for collector-emitter voltage VCEO of 50 V and output current IO up to 500 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-323-3 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-base voltage (open emitter) | VCBO | 50 | V | open emitter | 3 | ||
| Collector-emitter voltage (open base) | VCEO | 50 | V | open base | 3 | ||
| Emitter-base voltage, PDTD123EU | VEBO | 10 | V | open collector; PDTD123EU | 3 | ||
| Input voltage, PDTD123EU | VI | -10 | 12 | V | PDTD123EU | 3 | |
| Output current | IO | 500 | mA | 3 | |||
| Total power dissipation | Ptot | 300 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint [1] | 4 | ||
| Total power dissipation | Ptot | 425 | mW | Tamb ≤ 25 °C; FR4 PCB, 4-layer copper, standard footprint [2] | 4 | ||
| Junction temperature | Tj | 175 | °C | 4 | |||
| Ambient temperature | Tamb | -55 | 175 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 175 | °C | 4 | ||
| Thermal resistance from junction to ambient | Rth(j-a) | 500 | K/W | in free air; FR4 PCB, single-sided copper [1] | 4 | ||
| Thermal resistance from junction to ambient | Rth(j-a) | 353 | K/W | in free air; FR4 PCB, 4-layer copper [2] | 4 | ||
| Collector-base cut-off current | ICBO | 100 | nA | VCB = 40 V; IE = 0 A | 6 | ||
| Collector-emitter cut-off current | ICEO | 0.5 | A | VCE = 50 V; IB = 0 A | 6 | ||
| Emitter-base cut-off current, PDTD123EU | IEBO | 2 | mA | VEB = 5 V; IC = 0 A | 6 | ||
| DC current gain, PDTD123EU | hFE | 40 | VCE = 5 V; IC = 50 mA | 6 | |||
| Collector-emitter saturation voltage | VCEsat | 100 | mV | IC = 50 mA; IB = 2.5 mA | 6 | ||
| Off-state input voltage, PDTD123EU | VI(off) | 0.6 | 1.1 | 1.8 | V | VCE = 5 V; IC = 100 A | 6 |
| On-state input voltage, PDTD123EU | VI(on) | 1 | 1.5 | 2 | V | VCE = 0.3 V; IC = 20 mA | 6 |
| Bias resistor 1 (input), PDTD123EU | R1 | 1.54 | 2.2 | 2.86 | k | 7 | |
| Bias resistor ratio R2/R1, PDTD123EU | R2/R1 | 0.9 | 1 | 1.1 | 7 |
CAD (KiCad official)
- Symbol:
PDTD123EUX - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SOT-323-3 (KiCad packages3D, STEP)
- 3D model files:
pdtd123eux-etched.step/pdtd123eux-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pdtd123eux.step/pdtd123eux.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (27 pp, sha256
e811e4a5c607425e, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).