component
PDTC144EU
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-323. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPDTC144EU
Nexperia · Digital Transistors · SOT-323
PDTC144EU from Nexperia, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | input | Input (base) pin of the bias network, with the input voltage limited to -10 V to 40 V per the Limiting values table. |
| 2 | GND | power_in | Ground (emitter) pin, the common reference of the transistor, with the emitter-base voltage rated at 10 V maximum (VEBO). |
| 3 | O | output | Output (collector) pin, rated at 50 V maximum collector-emitter voltage (VCEO) and 100 mA maximum output current (IO). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO | 50 | V | open emitter | 3 | ||
| collector-emitter voltage | VCEO | 50 | V | open base | 3 | ||
| emitter-base voltage | VEBO | 10 | V | open collector | 3 | ||
| input voltage | VI | -10 | 40 | V | 3 | ||
| output current | IO | 100 | mA | 3 | |||
| total power dissipation | Ptot | 200 | mW | Tamb ≤ 25 °C | 3 | ||
| junction temperature | Tj | 150 | °C | 3 | |||
| ambient temperature | Tamb | -65 | 150 | °C | 3 | ||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| thermal resistance from junction to ambient | Rth(j-a) | 625 | K/W | in free air | 4 | ||
| collector-base breakdown voltage | V(BR)CBO | 50 | V | IC = 100 µA; IE = 0 A; Tamb = 25 °C | 5 | ||
| collector-emitter breakdown voltage | V(BR)CEO | 50 | V | IC = 2 mA; IB = 0 A; Tamb = 25 °C | 5 | ||
| collector-base cut-off current | ICBO | 100 | nA | VCB = 50 V; IE = 0 A; Tamb = 25 °C | 5 | ||
| collector-emitter cut-off current | ICEO | 100 | nA | VCE = 30 V; IB = 0 A; Tamb = 25 °C | 5 | ||
| collector-emitter cut-off current | ICEO | 5 | µA | VCE = 30 V; IB = 0 A; Tj = 150 °C | 5 | ||
| emitter-base cut-off current | IEBO | 90 | µA | VEB = 5 V; IC = 0 A; Tamb = 25 °C | 5 | ||
| DC current gain | hFE | 80 | VCE = 5 V; IC = 5 mA; Tamb = 25 °C | 5 | |||
| collector-emitter saturation voltage | VCEsat | 150 | mV | IC = 10 mA; IB = 0.5 mA; Tamb = 25 °C | 5 | ||
| off-state input voltage | VI(off) | 1.2 | 0.8 | V | VCE = 5 V; IC = 100 µA; Tamb = 25 °C | 5 | |
| on-state input voltage | VI(on) | 3 | 1.6 | V | VCE = 0.3 V; IC = 2 mA; Tamb = 25 °C | 5 | |
| bias resistor 1 (input) | R1 | 33 | 47 | 61 | kΩ | 5 | |
| bias resistor ratio | R2/R1 | 0.8 | 1 | 1.2 | 5 | ||
| collector capacitance | Cc | 2.5 | pF | VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C | 5 |
CAD (KiCad official)
- Symbol:
PDTC144EU - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files:
pdtc144eu-etched.step/pdtc144eu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pdtc144eu.step/pdtc144eu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (11 pp, sha256
e823bfb51eb33d51, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).