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PDTC115TT

Public Made by Adom

by adom

Nexperia Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PDTC115TT

Nexperia · Digital Transistors · SOT-23

PDTC115TT from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input (base) of the NPN transistor, connected through built-in bias resistor R1 = 100 kΩ (70 to 130 kΩ at 25 °C); VEBO max 5 V.
2 GND power_in Ground (emitter) of the NPN transistor.
3 O output Output (collector) of the NPN transistor; VCEO max 50 V and output current IO max 100 mA.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
collector-emitter voltage (quick ref) VCEO 50 V open base 1
output current (quick ref) IO 100 mA 1
bias resistor 1 (input) R1 70 100 130 kΩ Tamb = 25 °C 3
collector-base cut-off current ICBO 100 nA VCB = 50 V; IE = 0 A; Tamb = 25 °C 3
collector-emitter cut-off current ICEO 100 nA VCE = 30 V; IB = 0 A; Tamb = 25 °C 3
collector-emitter cut-off current ICEO 5 µA VCE = 30 V; IB = 0 A; Tj = 150 °C 3
emitter-base cut-off current IEBO 100 nA VEB = 5 V; IC = 0 A; Tamb = 25 °C 3
DC current gain hFE 100 VCE = 5 V; IC = 1 mA; Tamb = 25 °C 3
collector-emitter saturation voltage VCEsat 150 mV IC = 5 mA; IB = 0.25 mA; Tamb = 25 °C 3
collector capacitance Cc 2.5 pF VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C 3
collector-base voltage VCBO 50 V open emitter 2
collector-emitter voltage VCEO 50 V open base 2
emitter-base voltage VEBO 5 V open collector 2
output current IO 100 mA 2
peak collector current ICM 100 mA 2
total power dissipation Ptot 250 mW Tamb ≤ 25 °C; FR4 PCB, single-sided copper, tin-plated, standard footprint 2
junction temperature Tj 150 °C 2
ambient temperature Tamb -65 150 °C 2
storage temperature Tstg -65 150 °C 2
thermal resistance from junction to ambient Rth(j-a) 500 K/W in free air; FR4 PCB, single-sided copper, tin-plated, standard footprint 2

CAD (KiCad official)

  • Symbol: PDTC115TT
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdtc115tt-etched.step / pdtc115tt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdtc115tt.step / pdtc115tt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (8 pp, sha256 7062bce3feb6b5ec, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF