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PDTB123YT

Nexperia · Digital Transistors · SOT-23

PDTB123YT from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input (base) of the resistor-equipped PNP transistor, with bias resistor R1 = 2.2 kΩ (±10 %); the input voltage is limited to +5 V positive and -20 V negative.
2 GND power_in Ground (emitter) connection of the transistor; the datasheet specifies it as the emitter terminal and gives no separate voltage limit for this pin.
3 O output Output (collector) of the transistor, rated for a maximum output current of -500 mA with VCEO of -50 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PDTB123YT
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdtb123yt-etched.step / pdtb123yt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdtb123yt.step / pdtb123yt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (9 pp, sha256 4f13370a576e4c44, retrieved 2026-10-09, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF