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Contents

README

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PDTA144ET

Nexperia · Digital Transistors · SOT-23

PDTA144ET from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input terminal (base) with input voltage range -40 to +10 V connected through 47 kΩ resistor R1.
2 G power_in Ground and emitter terminal of the PNP transistor.
3 O output Collector terminal supporting maximum collector-emitter voltage of -50 V and maximum output current of -100 mA.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PDTA144ET
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdta144et-etched.step / pdta144et-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdta144et.step / pdta144et.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 5f2bb579575d3264, retrieved 2026-09-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF