component
PDTA143ET
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPDTA143ET
Nexperia · Digital Transistors · SOT-23
PDTA143ET from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | input | Input (base) pin; it connects to the transistor base through the built-in bias resistor R1 (4.7 kΩ), and the datasheet gives an input voltage limit of -30 V to 10 V. |
| 2 | GND | power_in | Ground (emitter) pin; it is the transistor emitter, and the built-in bias resistor R2 (4.7 kΩ) is connected between the base and this pin. |
| 3 | O | output | Output (collector) pin; the datasheet limits the output current IO to -100 mA and the collector-emitter voltage VCEO to -50 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
PDTA143ET - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
pdta143et-etched.step/pdta143et-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pdta143et.step/pdta143et.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
472793e5bb2f8565, retrieved 2026-10-09, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).