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Contents

README

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PDTA123JT

Nexperia · Digital Transistors · SOT-23

PDTA123JT from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 input input Input terminal connected through bias resistor R1 (2.2 kΩ nominal) to the base of the built-in PNP transistor; accepts input voltage from -12 V to +5 V.
2 GND power_in Ground and emitter terminal of the built-in PNP transistor.
3 output output Collector output terminal capable of sourcing up to 100 mA output current with maximum collector-emitter voltage VCEO of 50 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PDTA123JT
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdta123jt-etched.step / pdta123jt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdta123jt.step / pdta123jt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 d942702c3c615b73, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF