Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

PDTA114YT

Nexperia · Digital Transistors · SOT-23

PDTA114YT from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input (base) terminal; accepts input voltage from -40 V to 6 V to control transistor operation.
2 G power_in Ground connection (emitter terminal).
3 O output Output (collector) terminal; supports -100 mA maximum output current at -50 V collector-emitter voltage.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: PDTA114YT
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdta114yt-etched.step / pdta114yt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdta114yt.step / pdta114yt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 8b7a1e403f08d3f1, retrieved 2026-09-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF