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PDTA113ET

Public Made by Adom

by adom

Nexperia Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PDTA113ET

Nexperia · Digital Transistors · SOT-23

PDTA113ET from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input (base) of the resistor-equipped transistor, with bias resistor R1 = 1 kΩ on this pin, and input voltage limited to -10 V to 10 V per Table 5.
2 GND power_in Ground (emitter) of the transistor, serving as the common reference for the bias resistor network.
3 O output Output (collector) of the transistor, with output current limited to -100 mA and peak collector current limited to -100 mA per Table 5.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
collector-base voltage (open emitter) VCBO -50 V open emitter 2
collector-emitter voltage (open base) VCEO -50 V open base 2
emitter-base voltage (open collector) VEBO -10 V open collector 2
input voltage VI -10 10 V 2
output current IO -100 mA 2
peak collector current ICM -100 mA 2
total power dissipation Ptot 250 mW Tamb ≤ 25 °C; device mounted on FR4 PCB, single-sided copper, tin-plated, standard footprint 2
junction temperature Tj 150 °C 2
ambient temperature Tamb -65 150 °C 2
storage temperature Tstg -65 150 °C 2
thermal resistance from junction to ambient Rth(j-a) 500 K/W in free air; device mounted on FR4 PCB, single-sided copper, tin-plated and standard footprint 3
collector-base cut-off current ICBO -100 nA VCB = -50 V; IE = 0 A; Tamb = 25 °C 3
collector-emitter cut-off current ICEO -100 nA VCE = -30 V; IB = 0 A; Tamb = 25 °C 3
collector-emitter cut-off current ICEO -5 µA VCE = -30 V; IB = 0 A; Tj = 150 °C 3
emitter-base cut-off current IEBO -4 mA VEB = -5 V; IC = 0 A; Tamb = 25 °C 3
DC current gain hFE 30 VCE = -5 V; IC = -40 mA; Tamb = 25 °C 3
collector-emitter saturation voltage VCEsat -150 mV IC = -30 mA; IB = -1.5 mA; Tamb = 25 °C 3
off-state input voltage VI(off) -1.3 -0.5 V VCE = -5 V; IC = -100 µA; Tamb = 25 °C 3
on-state input voltage VI(on) -2 -1.7 V VCE = -300 mV; IC = -20 mA; Tamb = 25 °C 3
bias resistor 1 (input) R1 0.7 1 1.3 kΩ 3
bias resistor ratio R2/R1 0.8 1 1.2 Tamb = 25 °C 3
collector capacitance Cc 2 pF VCB = -10 V; IE = 0 A; ie = 0 A; f = 1 MHz; Tamb = 25 °C 3

CAD (KiCad official)

  • Symbol: PDTA113ET
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: pdta113et-etched.step / pdta113et-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pdta113et.step / pdta113et.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (10 pp, sha256 2240276408f3260f, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF