component

PCMD3180IRTWR

Public Made by Adom

by adom

TI(德州仪器) , QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenticpcmd3180irtwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7h ago
viewers pcmd3180irtwr: viewers · Ray 7h ago
package.json Publish 0.1.0 · Ray 7h ago
page.json Set visibility: public · Ray 7h ago
pcmd3180irtwr-etched.glb Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr-etched.step pcmd3180irtwr: factory component page (tier=lcsc) · Ray 7h ago
pcmd3180irtwr-hero.glb pcmd3180irtwr: hero GLB from the etched model (keeps the MPN mark) · Ray 7h ago
pcmd3180irtwr-hero.overlay.json Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr.glb Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr.kicad_mod Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr.kicad_sym Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr.lbr Publish 0.1.0 · Ray 7h ago
pcmd3180irtwr.step Publish 0.1.0 · Ray 7h ago
README.md Publish 0.1.0 · Ray 7h ago

PCMD3180IRTWR

TI(德州仪器) · IC · QFN-24-EP(4x4)

PCMD3180IRTWR from TI(德州仪器), in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog power supply, 1.8V or 3.3V nominal (3.0V to 3.6V for 3.3V operation, 1.7V to 1.9V for 1.8V operation).
2 AREG power_out Analog on-chip regulator output (1.8V nominal) or external 1.8V analog supply input; connect 10µF and 0.1µF low-ESR capacitors in parallel to AVSS.
3 VREF power_in Analog reference voltage filter output; connect a 1µF capacitor to AVSS.
4 AVSS power_in Analog ground; short directly to the board ground plane.
5 MICBIAS power_out MICBIAS output; connect a 1µF capacitor to AVSS.
6 PDMDIN1_GPI1 input PDM microphone data input 1 or general-purpose digital input 1 (also digital microphone data, PLL input clock source, and so forth).
7 PDMCLK1_GPO1 output PDM microphone clock output 1 or general-purpose digital output 1 (also digital microphone clock, interrupt, and so forth).
8 PDMDIN2_GPI2 input PDM microphone data input 2 or general-purpose digital input 2 (also digital microphone data, PLL input clock source, and so forth).
9 PDMCLK2_GPO2 output PDM microphone clock output 2 or general-purpose digital output 2 (also digital microphone clock, interrupt, and so forth).
10 PDMDIN3_GPI3 input PDM microphone data input 3 or general-purpose digital input 3 (also digital microphone data, PLL input clock source, and so forth).
11 PDMCLK3_GPO3 output PDM microphone clock output 3 or general-purpose digital output 3 (also digital microphone clock, interrupt, and so forth).
12 PDMDIN4_GPI4 input PDM microphone data input 4 or general-purpose digital input 4 (also digital microphone data, PLL input clock source, and so forth).
13 PDMCLK4_GPO4 output PDM microphone clock output 4 or general-purpose digital output 4 (also digital microphone clock, interrupt, and so forth).
14 SHDNZ input Active-low device hardware shutdown and reset; keep low at least 1ms after shutdown before release.
15 ADDR1_MISO bidirectional I2C slave address A1 pin in I2C operation; SPI slave output pin in SPI operation.
16 ADDR0_SCLK input I2C slave address A0 pin in I2C operation; SPI serial bit clock in SPI operation.
17 SCL_MOSI input I2C control bus clock pin in I2C operation; SPI slave input pin in SPI operation.
18 SDA_SSZ bidirectional I2C control bus data pin in I2C operation; SPI slave-select pin in SPI operation.
19 IOVDD power_in Digital I/O power supply, 1.8V or 3.3V nominal (1.65V to 1.95V or 3.0V to 3.6V).
20 GPIO1 bidirectional General-purpose digital input/output 1 (also digital microphone clock or data, PLL input clock source, interrupt, and so forth).
21 SDOUT output Audio serial data interface bus output.
22 BCLK bidirectional Audio serial data interface bus bit clock.
23 FSYNC bidirectional Audio serial data interface bus frame synchronization signal.
24 DREG power_out Digital regulator output for the digital core supply (1.5V nominal); connect 10µF and 0.1µF low-ESR capacitors in parallel to VSS.
25 Thermal Pad (VSS) power_in Thermal pad shorted to internal device ground; short directly to the board ground plane.

Key specifications

Parameter Value
Manufacturer TI(德州仪器)
Package QFN-24-EP(4x4)
Category
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS supply voltage AVDD -0.3 3.9 V 5
AREG to AVSS supply voltage AREG -0.3 2 V 5
IOVDD to VSS supply voltage IOVDD -0.3 3.9 V 5
Ground voltage difference AVSS to VSS -0.3 0.3 V 5
Operating ambient temperature (abs max) TA -40 125 °C 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V Human-body model per ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -500 500 V Charged-device model per JESD22C101 5
Analog supply voltage, 3.3V operation AVDD 3 3.3 3.6 V AREG generated using on-chip regulator 5
Analog supply voltage, 1.8V operation AVDD, AREG 1.7 1.8 1.9 V AREG internal regulator shutdown 5
IO supply voltage, 3.3V operation IOVDD 3 3.3 3.6 V 5
IO supply voltage, 1.8V operation IOVDD 1.65 1.8 1.95 V 5
Operating ambient temperature TA -40 125 °C 5
MCLK input clock frequency 36.864 MHz GPIOx or GPIx used as MCLK input 5
I2C bus capacitance, standard/fast-mode Cb 400 pF SCL and SDA, standard-mode and fast-mode 5
I2C bus capacitance, fast-mode plus Cb 550 pF SCL and SDA, fast-mode plus 5
Junction-to-ambient thermal resistance RθJA 32.6 °C/W RTW (WQFN) 24 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 25 °C/W 6
Junction-to-board thermal resistance RθJB 11.9 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.9 °C/W 6
Digital volume control range -100 27 dB Programmable 0.5dB steps 6
PDMCLKx output rate 0.7056 6.144 MHz Programmable 6
Output data sample rate 7.35 768 kHz Programmable 6
Output data sample word length 16 32 Bits Programmable 6
Low-level input threshold SHDNZ VIL(SHDNZ) -0.3 V SHDNZ pin (max is 0.25 x IOVDD) 6
Low-level input threshold, IOVDD 3.3V VIL -0.3 0.8 V All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 3.3V operation 6
Low-level input threshold, IOVDD 1.8V VIL -0.3 V All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 1.8V operation (max is 0.35 x IOVDD) 6
High-level input threshold, IOVDD 3.3V VIH 2 V All digital pins except PDMDINx_GPIx, SDA and SCL, IOVDD 3.3V operation (max is IOVDD + 0.3) 6
Low-level output voltage, IOVDD 1.8V VOL 0.45 V All digital pins except PDMCLKx_GPOx, SDA and SCL, IOL = -2mA, IOVDD 1.8V operation 6
Low-level output voltage, IOVDD 3.3V VOL 0.4 V All digital pins except PDMCLKx_GPOx, SDA and SCL, IOL = -2mA, IOVDD 3.3V operation 6
High-level output voltage, IOVDD 3.3V VOH 2.4 V All digital pins except PDMCLKx_GPOx, SDA and SCL, IOH = 2mA, IOVDD 3.3V operation 7
Low-level input threshold I2C VIL(I2C) -0.5 V SDA and SCL (max is 0.3x IOVDD) 7
Low-level output voltage SDA, IOVDD > 2V VOL1(I2C) 0.4 V SDA, IOL(I2C) = -3mA, IOVDD > 2V 7
Low-level output current SDA, standard/fast-mode IOL(I2C) 3 mA SDA, VOL(I2C) = 0.4V, standard-mode or fast-mode 7
Low-level output current SDA, fast-mode plus IOL(I2C) 20 mA SDA, VOL(I2C) = 0.4V, fast-mode plus 7
Input logic-low leakage IIL -5 0.1 5 µA All digital pins except PDMDINx_GPIx pins, input = 0V 7
Input logic-high leakage IIH -5 0.1 5 µA All digital pins except PDMDINx_GPIx pins, input = IOVDD 7
Low-level input threshold PDMDINx_GPIx, AVDD 3.3V VIL(GPIx) -0.3 0.8 V All PDMDINx_GPIx digital pins, AVDD 3.3V operation 7
High-level input threshold PDMDINx_GPIx, AVDD 3.3V VIH(GPIx) 2 V All PDMDINx_GPIx digital pins, AVDD 3.3V operation (max is AVDD + 0.3) 7
Low-level output voltage GPOx, AVDD 1.8V VOL(GPOx) 0.45 V All PDMCLKx_GPOx digital pins, IOL = -2mA, AVDD 1.8V operation 7
Low-level output voltage GPOx, AVDD 3.3V VOL(GPOx) 0.4 V All PDMCLKx_GPOx digital pins, IOL = -2mA, AVDD 3.3V operation 7
High-level output voltage GPOx, AVDD 3.3V VOH(GPOx) 2.4 V All PDMCLKx_GPOx digital pins, IOH = 2mA, AVDD 3.3V operation 7
Input leakage PDMDINx_GPIx, input = 0V IIL(GPIx) -5 0.1 5 µA All PDMDINx_GPIx digital pins, input = 0V 7
Input leakage PDMDINx_GPIx, input = AVDD IIH(GPIx) -5 0.1 5 µA All PDMDINx_GPIx digital pins, input = AVDD 7
SNR, 5th order PDM SNR 128 dB No signal, input generated using 5th order PDM modulator, A-weighted 6
SNR, 4th order PDM SNR 118 dB No signal, input generated using 4th order PDM modulator, A-weighted 6
Dynamic range, 5th order PDM DR 127 dB -60dB full-scale signal input, 5th order PDM modulator 6
Dynamic range, 4th order PDM DR 117 dB -60dB full-scale signal input, 4th order PDM modulator 6
Digital HPF cutoff frequency 12 Hz First-order IIR filter, -3dB point (default setting) 6
Input capacitance CIN 5 pF All digital pins 7
Pulldown resistance RPD 20 kΩ Digital I/O pins when asserted on 7
IAVDD hardware shutdown, AVDD 3.3V IAVDD 1 µA SHDNZ = 0, AVDD = 3.3V 7
IAVDD sleep mode, AVDD 3.3V IAVDD 5 µA All external clocks stopped, AVDD = 3.3V 7
IAVDD 8-channel recording, AVDD 3.3V IAVDD 11.9 mA fS = 48kHz, PDMCLKx = 64 × fS, PLL on, BCLK = 256 × fS, AVDD = 3.3V 8
IAVDD 8-channel recording, AVDD 1.8V IAVDD 11.3 mA AVDD = 1.8V, external AREG supply (AREG shorted to AVDD) 8
IAVDD 4-channel recording, AVDD 3.3V IAVDD 7.2 mA fS = 16kHz, PDMCLKx = 96 × fS, PLL on, BCLK = 256 × fS, AVDD = 3.3V 8
I2C SCL frequency, fast-mode plus fSCL 0 1000 kHz Fast-mode plus 9
SPI SCLK period t(SCLK) 40 ns 10
BCLK period t(BCLK) 40 ns 10
PDMCLK clock frequency f(PDMCLK) 0.768 6.144 MHz 11

CAD (KiCad official)

  • Symbol: PCMD3180IRTWR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: pcmd3180irtwr-etched.step / pcmd3180irtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcmd3180irtwr.step / pcmd3180irtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI(德州仪器) datasheet (117 pp, sha256 a0608fc99e10aad9, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF