component
PCM5101APW
Public Made by Adomby adom
Texas Instruments ADCs/DACs - Special Purpose, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPCM5101APW
Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-20
PCM5101APW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPVDD | power_in | Charge pump power supply, 3.3 V |
| 2 | CAPP | output | Charge pump flying capacitor terminal for positive rail |
| 3 | CPGND | power_in | Charge pump ground |
| 4 | CAPM | output | Charge pump flying capacitor terminal for negative rail |
| 5 | VNEG | output | Negative charge pump rail terminal for decoupling, -3.3 V |
| 6 | OUTL | output | Analog output from DAC left channel |
| 7 | OUTR | output | Analog output from DAC right channel |
| 8 | AVDD | power_in | Analog power supply, 3.3 V |
| 9 | AGND | power_in | Analog ground |
| 10 | DEMP | input | De-emphasis control for 44.1-kHz sampling rate with failsafe LVCMOS Schmitt trigger; Off (Low) / On (High) |
| 11 | FLT | input | Filter select with failsafe LVCMOS Schmitt trigger; Normal latency (Low) / Low latency (High) |
| 12 | SCK | input | System clock input supporting up to 50 MHz with failsafe LVCMOS Schmitt trigger |
| 13 | BCK | input | Audio data bit clock input with failsafe LVCMOS Schmitt trigger |
| 14 | DIN | input | Audio data input with failsafe LVCMOS Schmitt trigger |
| 15 | LRCK | input | Audio data word clock input with failsafe LVCMOS Schmitt trigger |
| 16 | FMT | input | Audio format selection with failsafe LVCMOS Schmitt trigger; I2S (Low) / Left-justified (High) |
| 17 | XSMT | input | Soft mute control with failsafe LVCMOS Schmitt trigger; Soft mute (Low) / soft un-mute (High) |
| 18 | LDOO | power_in | Internal logic supply rail terminal for decoupling with 0.1-µF capacitor or external 1.8 V supply terminal |
| 19 | DGND | power_in | Digital ground |
| 20 | DVDD | power_in | Digital power supply, 1.8 V or 3.3 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Data Acquisition |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
PCM5101APW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
pcm5101apw-etched.step/pcm5101apw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pcm5101apw.step/pcm5101apw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
a522083606b8e994, retrieved 2026-09-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).