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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

PCM3168APAPR

Texas Instruments · Audio Interface ICs · TQFP-64(10x10)

PCM3168APAPR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCOMAD	power_out	ADC analog common voltage decoupling output at 0.5 × VCCAD1 with 10 kΩ output impedance and ±1 μA source/sink capability.
2	AGNDAD2	power_in	Analog ground 2 for ADC.
3	VCCAD2	power_in	ADC analog power supply 2, 5 V.
4	RST	input	Reset and power-down control input with active low; 5-V tolerant Schmitt trigger with 50-kΩ typical internal pulldown resistor.
5	OVF	output	Overflow flag output for ADC indicating any six-channel ADC digital output exceeds full-scale range, held high for 1024 LRCKAD clock cycles.
6	LRCKAD	bidirectional	Audio data word clock input/output for ADC; input with Schmitt trigger and 50-kΩ pulldown in slave mode, output in master mode.
7	BCKAD	bidirectional	Audio data bit clock input/output for ADC; input with Schmitt trigger and 50-kΩ pulldown in slave mode, output in master mode.
8	DOUT1	output	Audio data digital output for ADC1 and ADC2 with 20 pF maximum load capacitance.
9	DOUT2	output	Audio data digital output for ADC3 and ADC4 with 20 pF maximum load capacitance.
10	DOUT3	output	Audio data digital output for ADC5 and ADC6 with 20 pF maximum load capacitance.
11	DGND2	power_in	Digital ground 2.
12	VDD2	power_in	Digital power supply 2, 3.3 V.
13	ZERO	output	Zero detect flag output for DAC indicating all eight-channel DAC digital inputs have continued as zero data for 1024 LRCKDA clock cycles.
14	VCCDA1	power_in	DAC analog power supply 1, 5 V.
15	VCOMDA	power_out	DAC voltage common decoupling output at 0.5 × VCCDA1 with 7.5 kΩ output impedance and ±1 μA source/sink capability.
16	AGNDDA1	power_in	Analog ground 1 for DAC.
17	VOUT8+	output	Positive analog output from DAC8 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
18	VOUT8-	output	Negative analog output from DAC8 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
19	VOUT7+	output	Positive analog output from DAC7 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
20	VOUT7-	output	Negative analog output from DAC7 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
21	VOUT6+	output	Positive analog output from DAC6 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
22	VOUT6-	output	Negative analog output from DAC6 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
23	VOUT5+	output	Positive analog output from DAC5 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
24	VOUT5-	output	Negative analog output from DAC5 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
25	VOUT4+	output	Positive analog output from DAC4 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
26	VOUT4-	output	Negative analog output from DAC4 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
27	VOUT3+	output	Positive analog output from DAC3 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
28	VOUT3-	output	Negative analog output from DAC3 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
29	VOUT2+	output	Positive analog output from DAC2 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
30	VOUT2-	output	Negative analog output from DAC2 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
31	VOUT1+	output	Positive analog output from DAC1 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
32	VOUT1-	output	Negative analog output from DAC1 with 1.6 × VCCDA1 VPP differential voltage capability and 0.5 × VCCDA1 V center voltage.
33	AGNDDA2	power_in	Analog ground 2 for DAC.
34	VCCDA2	power_in	DAC analog power supply 2, 5 V.
35	LRCKDA	bidirectional	Audio data word clock input/output for DAC; input with Schmitt trigger and 50-kΩ pulldown in slave mode, output in master mode.
36	BCKDA	bidirectional	Audio data bit clock input/output for DAC; input with Schmitt trigger and 50-kΩ pulldown in slave mode, output in master mode.
37	DIN1	input	Audio data input for DAC1 and DAC2.
38	DIN2	input	Audio data input for DAC3 and DAC4.
39	DIN3	input	Audio data input for DAC5 and DAC6.
40	DIN4	input	Audio data input for DAC7 and DAC8.
41	SCKI	input	System clock input operating at 2.048 to 36.864 MHz with 40% to 60% duty cycle; 5-V tolerant Schmitt trigger.
42	MC/SCL/FMT	input	SPI mode: master clock; I²C mode: serial clock; hardware mode: format select; 5-V tolerant Schmitt trigger.
43	MDI/SDA/DEMP	bidirectional	SPI mode: master data input; I²C mode: serial data open-drain; hardware mode: de-emphasis control; 5-V tolerant Schmitt trigger.
44	MDO/ADR1/MD1	tri_state	SPI mode: master data output with 3-state (Hi-Z) operation when chip select high; I²C mode: address select 1; hardware mode: mode select 1.
45	MS/ADR0/MD0	input	SPI mode: chip select; I²C mode: address select 0; hardware mode: mode select 0; 5-V tolerant Schmitt trigger with 50-kΩ typical internal pulldown resistor.
46	VDD1	power_in	Digital power supply 1, 3.3 V.
47	DGND1	power_in	Digital ground 1.
48	MODE	input	Control port mode selection; quad-state input (tied to VDD for SPI, pulled up for hardware single-ended, pulled down for hardware differential, tied to DGND for I²C) with 220 kΩ ±5% resistors.
49	VCCAD1	power_in	ADC analog power supply 1, 5 V.
50	AGNDAD1	power_in	Analog ground 1 for ADC.
51	VIN1-	input	Negative analog input to ADC1 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
52	VIN1+	input	Positive analog input to ADC1 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.
53	VIN2-	input	Negative analog input to ADC2 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
54	VIN2+	input	Positive analog input to ADC2 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.
55	VIN3-	input	Negative analog input to ADC3 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
56	VIN3+	input	Positive analog input to ADC3 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.
57	VIN4-	input	Negative analog input to ADC4 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
58	VIN4+	input	Positive analog input to ADC4 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.
59	VREFAD1	power_out	ADC analog reference voltage 1 decoupling output at VCCAD1 V; connect to 10 μF electrolytic capacitor to analog ground.
60	VREFAD2	power_out	ADC analog reference voltage 2 decoupling output at AGNDAD1 V; connect to 10 μF electrolytic capacitor to analog ground.
61	VIN5-	input	Negative analog input to ADC5 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
62	VIN5+	input	Positive analog input to ADC5 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.
63	VIN6-	input	Negative analog input to ADC6 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended mode selectable.
64	VIN6+	input	Positive analog input to ADC6 with 45 kΩ input impedance; differential 0.4 × VCCAD1 VRMS or single-ended 0.2 × VCCAD1 VRMS.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-64(10x10)
Category	Interface
Pins	64

CAD (KiCad official)

Symbol: PCM3168APAPR
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: pcm3168apapr-etched.step / pcm3168apapr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcm3168apapr.step / pcm3168apapr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (68 pp, sha256 af140cfec70f58f5, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF