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PCM1809IRTER

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TI(德州仪器) , WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PCM1809IRTER

TI(德州仪器) · IC · WQFN-20-EP(3x3)

PCM1809IRTER from TI(德州仪器), in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1P input Analog input 1P pin, used for the positive side of channel 1 differential or single-ended line/microphone input.
2 IN1M input Analog input 1M pin, which can be grounded directly for a single-ended channel 1 input.
3 IN2P input Analog input 2P pin, used for the positive side of channel 2 differential or single-ended line/microphone input.
4 IN2M input Analog input 2M pin, which can be grounded directly for a single-ended channel 2 input.
5 VSS power_in Analog supply ground pin that must be shorted directly to the board ground plane.
6 SDOUT output Audio serial data interface bus output.
7 BCLK bidirectional Audio serial data interface bus bit clock.
8 FSYNC bidirectional Audio serial data interface bus frame synchronization signal.
9 IOVDD power_in Digital I/O power supply, 1.8 V or 3.3 V nominal (1.65 to 1.95 V or 3.0 to 3.6 V).
10 VSS power_in Analog supply ground pin that must be shorted directly to the board ground plane.
11 MD1 input Device configuration mode select 1 pin, which also serves as the MCLK input in controller mode.
12 MD0 input Device configuration mode select 0 pin, which selects 256 × fS (low) or 512 × fS (high) MCLK in controller mode.
13 MSZ input Audio interface bus controller or target select pin.
14 DREG power_out Digital regulator output voltage for the digital core supply, 1.5 V nominal.
15 VSS power_in Analog supply ground pin that must be shorted directly to the board ground plane.
16 AVDD power_in Analog power supply, 3.3 V nominal (3.0 to 3.6 V).
17 AREG power_out Analog on-chip regulator output voltage for the analog supply, 1.8 V nominal.
18 VREF power_in Analog reference voltage filter output (2.75 V) that needs a minimum 1-µF capacitor to analog ground and no external load.
19 FMT0 input Audio interface format select pin referred to the AVDD supply.
20 VSS power_in Analog supply ground pin that must be shorted directly to the board ground plane.
21 VSS power_in Thermal pad shorted to internal device ground, to be shorted directly to the board ground plane.

Key specifications

Parameter Value
Manufacturer TI(德州仪器)
Package WQFN-20-EP(3x3)
Category
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS supply voltage AVDD -0.3 3.9 V 4
AREG to AVSS supply voltage AREG -0.3 2 V 4
IOVDD to VSS supply voltage IOVDD -0.3 3.9 V 4
Ground voltage difference AVSS to VSS -0.3 0.3 V 4
Analog input pins voltage to AVSS -0.3 3.9 V AVDD + 0.3 V max 4
Digital input pins voltage to VSS -0.3 V IOVDD + 0.3 V max 4
Operating ambient temperature TA -40 105 °C 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -500 500 V CDM per JESD22-C101 4
Analog supply voltage AVDD 3 3.3 3.6 V AVDD 3.3-V operation 4
IO supply voltage 3.3-V IOVDD 3 3.3 3.6 V IOVDD 3.3-V operation 4
IO supply voltage 1.8-V IOVDD 1.65 1.8 1.95 V IOVDD 1.8-V operation 4
Analog input pins and FMT0 voltage 0 3.6 V to VSS, max AVDD 4
Digital input pins voltage (except FMT0) 0 V to VSS, max IOVDD 4
Operating ambient temperature TA -40 105 °C 4
MCLK input clock frequency 36.864 MHz Digital input pin used as MCLK 4
Digital output load capacitance CL 20 50 pF 4
Junction-to-ambient thermal resistance RθJA 55.9 °C/W RTE (WQFN) 20 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 33.1 °C/W RTE (WQFN) 20 pins 4
Junction-to-board thermal resistance RθJB 23.4 °C/W RTE (WQFN) 20 pins 4
Junction-to-top characterization parameter ψJT 0.6 °C/W 5
Junction-to-board characterization parameter ψJB 23.3 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 16.7 °C/W 5
AC input impedance 10 kΩ Input pins INxP or INxM 5
Differential input full-scale AC signal voltage (AC-coupled) 2 VRMS AC-coupled input 5
SNR differential AC-coupled SNR 104 dB IN1 differential input selected and AC signal shorted to ground 5
DR differential AC-coupled DR 104 dB IN1 differential input selected and -60-dB full-scale AC signal input 5
THD+N differential AC-coupled THD+N -95 dB IN1 differential input selected and -1-dB full-scale AC signal input 5
SNR single-ended AC-coupled SNR 100 102 dB IN1 Single ended input with AC coupling on IN1P with IN1M ground and AC signal shorted to ground 5
DR single-ended AC-coupled DR 102 dB IN1 Single ended input with AC coupling on IN1P with IN1M ground and -60-dB full-scale AC signal input 5
THD+N single-ended AC-coupled THD+N -88 dB IN1 Single ended input with AC coupleing on IN1P with IN1M ground and -1-dB full-scale AC signal input 5
Output data sample rate 7.35 192 kHz 5
Interchannel isolation -124 dB -1-dB full-scale AC-signal input to non measurement channel 5
Interchannel gain mismatch 0.1 dB -6-dB full-scale AC-signal input 5
Gain drift 40.5 ppm/°C Across temperature range -40°C to 105°C 5
Interchannel phase mismatch 0.02 Degrees 1-kHz sinusoidal signal 6
Phase drift 0.0005 Degrees/°C 1-kHz sinusoidal signal, across temperature range -40°C to 105°C 6
PSRR differential PSRR 102 dB 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 6
PSRR single-ended PSRR 102 dB 100-mVPP, 1-kHz sinusoidal signal on AVDD, single ended input selected, 0-dB channel gain 6
Low-level input voltage, IOVDD 1.8 V VIL -0.3 0.3 V All digital pins except FMT0, IOVDD 1.8-V operation; max 0.30 × IOVDD 6
Low-level input voltage, IOVDD 3.3 V VIL -0.3 0.8 V All digital pins except FMT0, IOVDD 3.3-V operation 6
Low-level input voltage FMT0 VIL -0.3 0.8 V FMT0 Pin 6
High-level input voltage, IOVDD 3.3 V VIH 2.1 V All digital pins except FMT0, IOVDD 3.3-V operation; max IOVDD + 0.3 6
High-level input voltage FMT0 VIH 2.1 V FMT0 Pin; max AVDD + 0.3 6
Low-level output voltage, IOVDD 1.8 V VOL 0.45 V All digital pins, IOL = -2 mA, IOVDD 1.8-V operation 6
Low-level output voltage, IOVDD 3.3 V VOL 0.4 V All digital pins, IOL = -2 mA, IOVDD 3.3-V operation 6
High-level output voltage, IOVDD 3.3 V VOH 2.4 V All digital pins, IOH = 2 mA, IOVDD 3.3-V operation 6
Input logic-high leakage IIH -5 0.1 5 µA All digital pins, input = IOVDD 6
Input logic-low leakage IIL -5 0.1 5 µA All digital pins, input = 0 V 6
Input capacitance for digital inputs CIN 5 pF All digital pins 6
Pulldown resistance for digital I/O pins RPD 20 kΩ when asserted on 6
AVDD current, clocks disabled IAVDD 0.5 mA AVDD = 3.3 V, internal AREG 6
AVDD current, 2-channel at fS 16 kHz IAVDD 11.9 mA AVDD = 3.3 V, internal AREG, BCLK = 256 × fS 6
AVDD current, 2-channel at fS 48 kHz IAVDD 12.9 mA AVDD = 3.3 V, internal AREG, BCLK = 256 × fS 6
BCLK period t(BCLK) 40 ns 6
BCLK high pulse duration tH(BCLK) 25 ns 7
BCLK low pulse duration tL(BCLK) 25 ns 7
FSYNC setup time tSU(FSYNC) 8 ns 7
FSYNC hold time tHLD(FSYNC) 8 ns 7
BCLK rise time tr(BCLK) 10 ns 10% - 90% rise time 7
BCLK fall time tf(BCLK) 10 ns 90% - 10% fall time 7
BCLK to SDOUT delay td(SDOUT-BCLK) 3 18 ns 50% of BCLK to 50% of SDOUT 7
BCLK to FSYNC delay: controller mode td(FSYNC) 3 18 ns 50% of BCLK to 50% of FSYNC 7

CAD (KiCad official)

  • Symbol: PCM1809IRTER
  • Footprint: Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm
  • 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: pcm1809irter-etched.step / pcm1809irter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcm1809irter.step / pcm1809irter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI(德州仪器) datasheet (32 pp, sha256 d29bee15afa84467, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF