component
PCM1807PW
Public Made by Adomby adom
Texas Instruments ADCs/DACs - Special Purpose, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| viewers | 3h ago |
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| page.json | 3h ago |
| pcm1807pw-etched.glb | 3h ago |
| pcm1807pw-etched.step | 3h ago |
| pcm1807pw-hero.glb | 3h ago |
| pcm1807pw-hero.overlay.json | 3h ago |
| pcm1807pw.glb | 3h ago |
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| verification.json | 3h ago |
PCM1807PW
Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-14
PCM1807PW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage decoupling pin, set at 0.5 VCC, that needs external decoupling to AGND. |
| 2 | AGND | power_in | Analog ground reference for the converter. |
| 3 | VCC | power_in | Analog power supply, 5-V. |
| 4 | VDD | power_in | Digital power supply, 3.3-V. |
| 5 | DGND | power_in | Digital ground reference. |
| 6 | SCKI | input | System clock input at 256 fS, 384 fS or 512 fS; Schmitt-trigger input that is 5-V tolerant. |
| 7 | LRCK | bidirectional | Audio data latch enable input/output; Schmitt-trigger input with internal 50-kΩ typical pulldown, and minimum load applies when used for timing measurements. |
| 8 | BCK | bidirectional | Audio data bit clock input/output. |
| 9 | DOUT | output | Audio data digital output. |
| 10 | MD | input | Mode control data input; Schmitt-trigger input with internal 50-kΩ typical pulldown and 5-V tolerant. |
| 11 | MC | input | Mode control clock input; Schmitt-trigger input with internal 50-kΩ typical pulldown and 5-V tolerant. |
| 12 | MS | input | Mode control select input; Schmitt-trigger input with internal 50-kΩ typical pulldown and 5-V tolerant. |
| 13 | VINL | input | Single-ended analog input for the L-channel. |
| 14 | VINR | input | Single-ended analog input for the R-channel. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | VCC | -0.3 | 6.5 | V | 2 | ||
| Digital supply voltage | VDD | -0.3 | 4 | V | 2 | ||
| Ambient temperature under bias | TA | -40 | 125 | °C | 2 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Junction temperature | TJ | 150 | °C | 2 | |||
| Input current (any pins except supplies) | -10 | 10 | mA | 2 | |||
| Lead temperature (soldering) | 260 | °C | 5 s | 2 | |||
| Package temperature (reflow, peak) | 260 | °C | 2 | ||||
| Analog supply voltage | VCC | 4.5 | 5 | 5.5 | V | 2 | |
| Digital supply voltage | VDD | 2.7 | 3.3 | 3.6 | V | 2 | |
| Analog input voltage, full scale (-0 dB) | 3 | Vp-p | VCC = 5 V | 2 | |||
| Digital input clock frequency, system clock | 4.096 | 49.152 | MHz | 2 | |||
| Digital input clock frequency, sampling clock | 16 | 96 | kHz | 2 | |||
| Digital output load capacitance | 20 | pF | 2 | ||||
| Operating free-air temperature | TA | -40 | 85 | °C | 2 | ||
| Input logic level VIH(1) | VIH | 2 | VDC | Pins 7-9 and footnote 1; maximum printed as VDD | 3 | ||
| Input logic level VIL(1) | VIL | 0 | 0.8 | VDC | Pins 7-8 (footnote 1) | 3 | |
| Input logic level VIH(2)(3) | VIH | 2 | 5.5 | VDC | Pins 6, 10-12 (footnotes 2, 3) | 3 | |
| Input logic level VIL(2)(3) | VIL | 0 | 0.8 | VDC | Pins 6, 10-12 (footnotes 2, 3) | 3 | |
| Input logic current IIH(2) | IIH | -10 | 10 | µA | VIN = VDD | 3 | |
| Input logic current IIL(2) | IIL | -10 | 10 | µA | VIN = 0 V | 3 | |
| Input logic current IIH(1)(3) | IIH | 65 | 100 | µA | VIN = VDD | 3 | |
| Input logic current IIL(1)(3) | IIL | -10 | 10 | µA | VIN = 0 V | 3 | |
| Output logic level VOH(4) | VOH | 2.8 | VDC | IOUT = -4 mA | 3 | ||
| Output logic level VOL(4) | VOL | 0.5 | VDC | IOUT = 4 mA | 3 | ||
| Gain mismatch, channel-to-channel | -3 | 1 | 3 | % of FSR | 3 | ||
| Gain error | -6 | 3 | 6 | % of FSR | 3 | ||
| THD+N at VIN = -0.5 dB, fS = 48 kHz | THD+N | -93 | -87 | dB | VIN = -0.5 dB, fS = 48 kHz | 3 | |
| THD+N at VIN = -0.5 dB, fS = 96 kHz | THD+N | -87 | dB | VIN = -0.5 dB, fS = 96 kHz (footnote 6) | 3 | ||
| THD+N at VIN = -60 dB, fS = 48 kHz | THD+N | -37 | dB | VIN = -60 dB, fS = 48 kHz | 3 | ||
| THD+N at VIN = -60 dB, fS = 96 kHz | THD+N | -39 | dB | VIN = -60 dB, fS = 96 kHz (footnote 6) | 3 | ||
| Dynamic range, A-weighted, fS = 48 kHz | 95 | 99 | dB | fS = 48 kHz, A-weighted | 3 | ||
| Dynamic range, A-weighted, fS = 96 kHz | 101 | dB | fS = 96 kHz, A-weighted (footnote 6) | 3 | |||
| Signal-to-noise ratio, fS = 48 kHz | S/N | 95 | 99 | dB | fS = 48 kHz, A-weighted | 3 | |
| Signal-to-noise ratio, fS = 96 kHz | S/N | 101 | dB | fS = 96 kHz, A-weighted (footnote 6) | 3 | ||
| Channel separation, fS = 48 kHz | 93 | 97 | dB | fS = 48 kHz | 3 | ||
| Channel separation, fS = 96 kHz | 91 | dB | fS = 96 kHz (footnote 6) | 3 | |||
| Sampling frequency fS | fS | 16 | 48 | 96 | kHz | 3 | |
| System clock frequency 256 fS | fSCLK | 4.096 | 12.288 | 24.576 | MHz | 256 fS | 3 |
| System clock frequency 384 fS | fSCLK | 6.144 | 18.432 | 36.864 | MHz | 384 fS | 3 |
| System clock frequency 512 fS | fSCLK | 8.192 | 24.576 | 49.152 | MHz | 512 fS | 3 |
| Input impedance | 60 | kΩ | 3 | ||||
| Antialiasing filter frequency response -3 dB | 1.3 | MHz | -3 dB | 3 | |||
| Voltage range VCC | VCC | 4.5 | 5 | 5.5 | VDC | 4 | |
| Voltage range VDD | VDD | 2.7 | 3.3 | 3.6 | VDC | 4 | |
| Supply current ICC | ICC | 8.6 | 11 | mA | 4 | ||
| Supply current ICC powered down | ICC | 1 | µA | Powered down (footnote 8) | 4 | ||
| Supply current IDD fS = 48 kHz | IDD | 5.9 | 8 | mA | fS = 48 kHz (footnote 7) | 4 | |
| Supply current IDD fS = 96 kHz | IDD | 10.2 | mA | fS = 96 kHz (footnote 9) | 4 | ||
| Supply current IDD powered down | IDD | 80 | µA | Powered down (footnote 8) | 4 | ||
| Power dissipation operating fS = 48 kHz | 62 | 81 | mW | Operating, fS = 48 kHz | 4 | ||
| Power dissipation operating fS = 96 kHz | 77 | mW | Operating, fS = 96 kHz (footnote 9) | 4 | |||
| Power dissipation powered down | 270 | µW | Powered down (footnote 8) | 4 | |||
| Operation temperature | TA | -40 | 85 | °C | 4 | ||
| Thermal resistance | θJA | 170 | °C/W | 4 | |||
| System clock pulse duration, HIGH | tw(SCKH) | 8 | ns | 11 | |||
| System clock pulse duration, LOW | tw(SCKL) | 8 | ns | 11 |
CAD (KiCad official)
- Symbol:
PCM1807PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
pcm1807pw-etched.step/pcm1807pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pcm1807pw.step/pcm1807pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
ee9c0c00847e1d1d, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).