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Contents

README

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PCM1804DBR

Texas Instruments · ADCs/DACs - Special Purpose · SSOP-28-208mil

PCM1804DBR from Texas Instruments, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREFL passive L-channel voltage reference output requiring external decoupling capacitors to AGND.
2 AGNDL power_in Analog ground reference for VREFL.
3 VCOML passive L-channel common-mode bias voltage, 2.5 V dc.
4 VINL+ input L-channel positive analog input for differential input range of ±2.5 V.
5 VINL− input L-channel negative analog input for differential input range of ±2.5 V.
6 FMT0 input Audio data format control bit 0 with Schmitt-trigger input, 51 kΩ internal pulldown, 5 V tolerant.
7 FMT1 input Audio data format control bit 1 with Schmitt-trigger input, 51 kΩ internal pulldown, 5 V tolerant.
8 S/M input Master/slave mode selection (low = master, high = slave) with Schmitt-trigger, 51 kΩ internal pulldown.
9 OSR0 input Oversampling ratio control bit 0 with Schmitt-trigger input, 51 kΩ internal pulldown, 5 V tolerant.
10 OSR1 input Oversampling ratio control bit 1 with Schmitt-trigger input, 51 kΩ internal pulldown, 5 V tolerant.
11 OSR2 input Oversampling ratio control bit 2 with Schmitt-trigger input, 51 kΩ internal pulldown, 5 V tolerant.
12 BYPAS input High-pass filter bypass control (low = enabled, high = disabled) with Schmitt-trigger input.
13 DGND power_in Digital ground reference.
14 VDD power_in Digital power supply input, 3.0 V to 3.6 V operating range.
15 DATA/DSDR output Audio data output carrying left and right stereo channels in PCM mode or R-channel in DSD mode.
16 BCK/DSDL bidirectional Bit clock input/output in PCM mode (input in slave, output in master) and L-channel audio data output in DSD mode.
17 LRCK/DSDBCK bidirectional Sampling clock input/output in PCM and DSD modes (input in slave, output in master); Schmitt-trigger in slave mode.
18 SCKI input System clock input with frequency range 8.192 MHz to 36.864 MHz; Schmitt-trigger, 5 V tolerant.
19 RST input Reset and power-down control input (active-low) with Schmitt-trigger, 51 kΩ internal pulldown, 5 V tolerant.
20 OVFR output R-channel overflow flag output in PCM mode; asserted high when analog input exceeds full-scale range.
21 OVFL output L-channel overflow flag output in PCM mode; asserted high when analog input exceeds full-scale range.
22 VCC power_in Analog power supply input, 4.75 V to 5.25 V operating range.
23 AGND power_in Analog ground reference.
24 VINR− input R-channel negative analog input for differential input range of ±2.5 V.
25 VINR+ input R-channel positive analog input for differential input range of ±2.5 V.
26 VCOMR passive R-channel common-mode bias voltage, 2.5 V dc.
27 AGNDR power_in Analog ground reference for VREFR.
28 VREFR passive R-channel voltage reference output requiring external decoupling capacitors to AGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28-208mil
Category Data Acquisition
Pins 28

CAD (KiCad official)

  • Symbol: PCM1804DBR
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: pcm1804dbr-etched.step / pcm1804dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcm1804dbr.step / pcm1804dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 3f38f0dcd2c1ba14, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF