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PCAL9555APW

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NXP Semicon I/O Expanders, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PCAL9555APW

NXP Semicon · I/O Expanders · TSSOP-24

PCAL9555APW from NXP Semicon, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INT output Interrupt output. Connect to VDD through a pull-up resistor.
2 A1 input Address input 1. Connect directly to VDD or VSS.
3 A2 input Address input 2. Connect directly to VDD or VSS.
4 P0_0 bidirectional Port 0 input/output 0.
5 P0_1 bidirectional Port 0 input/output 1.
6 P0_2 bidirectional Port 0 input/output 2.
7 P0_3 bidirectional Port 0 input/output 3.
8 P0_4 bidirectional Port 0 input/output 4.
9 P0_5 bidirectional Port 0 input/output 5.
10 P0_6 bidirectional Port 0 input/output 6.
11 P0_7 bidirectional Port 0 input/output 7.
12 VSS power_in Ground.
13 P1_0 bidirectional Port 1 input/output 0.
14 P1_1 bidirectional Port 1 input/output 1.
15 P1_2 bidirectional Port 1 input/output 2.
16 P1_3 bidirectional Port 1 input/output 3.
17 P1_4 bidirectional Port 1 input/output 4.
18 P1_5 bidirectional Port 1 input/output 5.
19 P1_6 bidirectional Port 1 input/output 6.
20 P1_7 bidirectional Port 1 input/output 7.
21 A0 input Address input 0. Connect directly to VDD or VSS.
22 SCL input Serial clock bus. Connect to VDD through a pull-up resistor.
23 SDA bidirectional Serial data bus. Connect to VDD through a pull-up resistor.
24 VDD power_in Supply voltage.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package TSSOP-24
Category Communication Interface Chip/UART/485/232
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VDD -0.5 6.5 V 25
input voltage VI -0.5 6.5 V 25
output voltage VO -0.5 6.5 V 25
input clamping current IIK 20 mA A0, A1, A2, SCL; VI <0V 25
output clamping current IOK 20 mA INT; VO <0V 25
input/output clamping current IIOK 20 mA P port; VO < 0 V or VO > VDD 25
LOW-level output current IOL 50 mA continuous; I/O port 25
LOW-level output current IOL 25 mA continuous; SDA, INT 25
HIGH-level output current IOH 25 mA continuous; P port 25
supply current IDD 160 mA 25
ground supply current ISS 200 mA 25
total power dissipation Ptot 200 mW 25
storage temperature Tstg -65 150 °C 25
maximum junction temperature Tj(max) 125 °C 25
supply voltage VDD 1.65 5.5 V 25
HIGH-level input voltage VIH 5.5 V SCL, SDA 25
LOW-level input voltage VIL -0.5 V SCL, SDA 25
HIGH-level output current IOH 10 mA P1_7 to P0_0 25
LOW-level output current IOL 25 mA P1_7 to P0_0 25
ambient temperature Tamb -40 85 °C operating in free air 25
transient thermal impedance from junction to ambient Zth(j-a) 88 K/W TSSOP24 package 25
input clamping voltage VIK 1.2 V II = 18 mA 26
power-on reset voltage VPOR 1.1 1.4 V VI =VDD or VSS; IO = 0 mA 26
HIGH-level output voltage VOH 1.2 V P port; IOH = 8 mA; CCX.X = 11b; VDD = 1.65 V 26
HIGH-level output voltage VOH 1.8 V P port; IOH = 8 mA; CCX.X = 11b; VDD = 2.3 V 26
HIGH-level output voltage VOH 2.6 V P port; IOH = 8 mA; CCX.X = 11b; VDD = 3 V 26
HIGH-level output voltage VOH 4.1 V P port; IOH = 8 mA; CCX.X = 11b; VDD = 4.5 V 26
HIGH-level output voltage VOH 1.1 V P port; IOH = 2.5 mA and CCX.X = 00b; IOH = 5 mA and CCX.X = 01b; IOH = 7.5 mA and CCX.X = 10b; IOH = 10 mA and CCX.X = 11b; VDD = 1.65 V 26
HIGH-level output voltage VOH 1.7 V P port; IOH = 2.5 mA and CCX.X = 00b; IOH = 5 mA and CCX.X = 01b; IOH = 7.5 mA and CCX.X = 10b; IOH = 10 mA and CCX.X = 11b; VDD = 2.3 V 26
HIGH-level output voltage VOH 2.5 V P port; IOH = 2.5 mA and CCX.X = 00b; IOH = 5 mA and CCX.X = 01b; IOH = 7.5 mA and CCX.X = 10b; IOH = 10 mA and CCX.X = 11b; VDD = 3 V 26
HIGH-level output voltage VOH 4 V P port; IOH = 2.5 mA and CCX.X = 00b; IOH = 5 mA and CCX.X = 01b; IOH = 7.5 mA and CCX.X = 10b; IOH = 10 mA and CCX.X = 11b; VDD = 4.5 V 26
LOW-level output voltage VOL 0.45 V P port; IOL = 8 mA; CCX.X = 11b; VDD = 1.65 V 26
LOW-level output voltage VOL 0.25 V P port; IOL = 8 mA; CCX.X = 11b; VDD = 2.3 V 26
LOW-level output voltage VOL 0.2 V P port; IOL = 8 mA; CCX.X = 11b; VDD = 4.5 V 26
LOW-level output voltage VOL 0.5 V P port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD = 1.65 V 26
LOW-level output voltage VOL 0.3 V P port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD = 2.3 V 26
LOW-level output current IOL 3 mA VOL = 0.4 V; VDD = 1.65 V to 5.5 V; SDA 26
LOW-level output current IOL 3 15 mA VOL = 0.4 V; VDD = 1.65 V to 5.5 V; INT 26
input current II 1 µA VDD = 1.65 V to 5.5 V; SCL, SDA; VI =VDD or VSS 26
HIGH-level input current IIH 1 µA P port; VI =VDD; VDD = 1.65 V to 5.5 V 26
LOW-level input current IIL 1 µA P port; VI =VSS; VDD = 1.65 V to 5.5 V 26
internal pull-up resistance Rpu(int) 50 100 150 kΩ input/output 26
internal pull-down resistance Rpd(int) 50 100 150 kΩ input/output 26
supply current (fSCL = 400 kHz) IDD 10 25 µA VDD = 3.6 V to 5.5 V; fSCL = 400 kHz; IO = 0 mA; I/O = inputs 27
supply current (fSCL = 400 kHz) IDD 6.5 15 µA VDD = 2.3 V to 3.6 V; fSCL = 400 kHz; IO = 0 mA; I/O = inputs 27
supply current (fSCL = 400 kHz) IDD 4 9 µA VDD = 1.65 V to 2.3 V; fSCL = 400 kHz; IO = 0 mA; I/O = inputs 27
supply current (fSCL = 0 kHz) IDD 1.5 7 µA VDD = 3.6 V to 5.5 V; fSCL = 0 kHz; IO = 0 mA; I/O = inputs 27
supply current (fSCL = 0 kHz) IDD 1 3.2 µA VDD = 2.3 V to 3.6 V; fSCL = 0 kHz; IO = 0 mA; I/O = inputs 27
supply current (fSCL = 0 kHz) IDD 0.5 1.7 µA VDD = 1.65 V to 2.3 V; fSCL = 0 kHz; IO = 0 mA; I/O = inputs 27
supply current with pull-ups enabled IDD 1.1 1.5 mA with pull-ups enabled; VI on P port = VSS; fSCL = 0 kHz; IO = 0 mA; VDD = 1.65 V to 5.5 V 27
additional quiescent supply current IDD 25 µA SCL, SDA; one input at VDD − 0.6 V; other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V 27
additional quiescent supply current IDD 80 µA P port, A0, A1, A2; one input at VDD − 0.6 V; other inputs at VDD or VSS; VDD = 1.65 V to 5.5 V 27

CAD (KiCad official)

  • Symbol: PCAL9555APW
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: pcal9555apw-etched.step / pcal9555apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcal9555apw.step / pcal9555apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (46 pp, sha256 76a60b066b420e86, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF