PCA9670BS from NXP Semicon, in a HVQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AD2	input	Address input 2 is one of three hardware address pins; it has no internal pull-up and must be tied to VDD, VSS, SCL or SDA, directly or through a resistor.
2	P0	bidirectional	Quasi-bidirectional I/O 0 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
3	P1	bidirectional	Quasi-bidirectional I/O 1 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
4	P2	bidirectional	Quasi-bidirectional I/O 2 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
5	P3	bidirectional	Quasi-bidirectional I/O 3 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
6	VSS	power_in	Supply ground; it must be connected to supply ground for proper operation and is connected to the exposed center pad, which must be soldered to a thermal pad on the board.
7	P4	bidirectional	Quasi-bidirectional I/O 4 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
8	P5	bidirectional	Quasi-bidirectional I/O 5 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
9	P6	bidirectional	Quasi-bidirectional I/O 6 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
10	P7	bidirectional	Quasi-bidirectional I/O 7 has latched outputs with 25 mA sink capability and a weak internal 100 µA pull-up when used as an input.
11	RESET	input	Active LOW reset input that initializes the I/Os as inputs with a weak internal pull-up.
12	SCL	input	Serial clock line of the 1 MHz Fm+ I2C-bus interface.
13	SDA	bidirectional	Serial data line of the 1 MHz Fm+ I2C-bus interface, with 30 mA sink capability for 4000 pF buses.
14	VDD	power_in	Supply voltage, operating from 2.3 V to 5.5 V, with 5.5 V tolerant I/Os held to VDD.
15	AD0	input	Address input 0 is one of three hardware address pins; it has no internal pull-up and must be tied to VDD, VSS, SCL or SDA, directly or through a resistor.
16	AD1	input	Address input 1 is one of three hardware address pins; it has no internal pull-up and must be tied to VDD, VSS, SCL or SDA, directly or through a resistor.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	HVQFN-16-EP(3x3)
Category	Interface ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
supply voltage	VDD	-0.5		6	V		18
supply current	IDD			100	mA		18
ground supply current	ISS			400	mA		18
input voltage	VI	-0.5		5.5	V	min referenced to VSS	18
input current	II			20	mA		18
output current	IO			50	mA	note 1: total package maximum output current is 400 mA	18
total power dissipation	Ptot			400	mW		18
power dissipation per output	P/out			100	mW		18
maximum junction temperature	Tj(max)			125	°C		18
storage temperature	Tstg	-65		150	°C		18
ambient temperature	Tamb	-40		85	°C	operating	18
supply voltage	VDD	2.3		5.5	V		19
supply current	IDD		266	500	µA	Operating mode; no load; VI =VDD or VSS; fSCL = 1 MHz; AD0, AD1, AD2 = static H or L	19
standby current	Istb		2.5	10	µA	Standby mode; no load; VI =VDD or VSS; fSCL = 0 kHz	19
power-on reset voltage	VPOR		1.8	2	V		19
LOW-level input voltage (SCL, SDA)	VIL	-0.5			V		19
HIGH-level input voltage (SCL, SDA)	VIH			5.5	V		19
LOW-level output current (SDA)	IOL	20			mA	VOL = 0.4 V; VDD = 2.3 V	19
LOW-level output current (SDA)	IOL	25			mA	VOL = 0.4 V; VDD = 3.0 V	19
LOW-level output current (SDA)	IOL	30			mA	VOL = 0.4 V; VDD = 4.5 V	19
leakage current (SCL, SDA)	IL	-1		1	µA	VI =VDD or VSS	19
input capacitance (SCL, SDA)	Ci		4	10	pF	VI =VSS	19
LOW-level input voltage (P0 to P7)	VIL	-0.5			V		19
HIGH-level input voltage (P0 to P7)	VIH			5.5	V		19
LOW-level output current (P0 to P7)	IOL	12	27		mA	VOL = 0.5 V; VDD = 2.3 V	19
LOW-level output current (P0 to P7)	IOL	17	35		mA	VOL = 0.5 V; VDD = 3.0 V	19
LOW-level output current (P0 to P7)	IOL	25	41		mA	VOL = 0.5 V; VDD = 4.5 V	19
total LOW-level output current	IOL(tot)			200	mA	VOL = 0.5 V; VDD = 4.5 V	19
HIGH-level output current (P0 to P7)	IOH	30	250	300	µA	VOH =VSS	19
transient boosted pull-up current	Itrt(pu)	0.5	1		mA	VOH =VSS; see Figure 13	19
input capacitance (P0 to P7)	Ci		3	10	pF		19
LOW-level input voltage (RESET)	VIL	-0.5		0.8	V		19
HIGH-level input voltage (RESET)	VIH	2		5.5	V		19
input leakage current (RESET)	ILI	-1		1	µA		19
input capacitance (RESET)	Ci		3	5	pF		19
LOW-level input voltage (AD0, AD1, AD2)	VIL	-0.5			V		19
HIGH-level input voltage (AD0, AD1, AD2)	VIH			5.5	V		19
input leakage current (AD0, AD1, AD2)	ILI	-1		1	µA		19
SCL clock frequency	fSCL	0		1000	kHz	Fast-mode Plus I2C-bus	20
bus free time between a STOP and START condition	tBUF	0.5			s	Fast-mode Plus I2C-bus	20
hold time (repeated) START condition	tHD;STA	0.26			s	Fast-mode Plus I2C-bus	20
set-up time for a repeated START condition	tSU;STA	0.26			s	Fast-mode Plus I2C-bus	20
set-up time for STOP condition	tSU;STO	0.26			s	Fast-mode Plus I2C-bus	20
data hold time	tHD;DAT	0			ns	Fast-mode Plus I2C-bus	20
data valid acknowledge time	tVD;ACK	0.05		0.45	s	Fast-mode Plus I2C-bus	20
data valid time	tVD;DAT	50		450	ns	Fast-mode Plus I2C-bus	20
data set-up time	tSU;DAT	50			ns	Fast-mode Plus I2C-bus	20
LOW period of the SCL clock	tLOW	0.5			s	Fast-mode Plus I2C-bus	20
HIGH period of the SCL clock	tHIGH	0.26			s	Fast-mode Plus I2C-bus	20
fall time of both SDA and SCL signals	tf			120	ns	Fast-mode Plus I2C-bus	20
rise time of both SDA and SCL signals	tr			120	ns	Fast-mode Plus I2C-bus	20
pulse width of spikes suppressed by input filter	tSP			50	ns	Fast-mode Plus I2C-bus	20
data output valid time	tv(Q)			4	s	CL ≤ 100 pF	20
data input set-up time	tsu(D)	0			s	CL ≤ 100 pF	20
data input hold time	th(D)	4			s	CL ≤ 100 pF	20
reset pulse width	tw(rst)	4			s		20
reset recovery time	trec(rst)	0			s		20
reset time	trst	100			s		20
thermal resistance from junction to ambient	Rth(j-a)		40		°C/W	HVQFN16 package	18

CAD (KiCad official)

Symbol: PCA9670BS
Footprint: Package_DFN_QFN:HVQFN-16-1EP_3x3mm_P0.5mm_EP1.5x1.5mm
3D model: HVQFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: pca9670bs-etched.step / pca9670bs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pca9670bs.step / pca9670bs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (35 pp, sha256 8115ce10c9c4a3a3, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

PCA9670BS

Verified PCA9670BS

Verification log 1 record

3D Model

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Datasheet

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