PCA9538PW from NXP Semicon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A0	input	Address input 0 sets one of the fixed hardware-selectable bits of the I2C-bus target address (1 1 1 0 0 A1 A0).
2	A1	input	Address input 1 sets one of the fixed hardware-selectable bits of the I2C-bus target address (1 1 1 0 0 A1 A0).
3	RESET	input	Active LOW reset input that holds the registers and I2C-bus state machine in their default state while held LOW for at least tw(rst), and requires a pullup resistor to VDD if unused.
4	IO0	bidirectional	Input/output 0 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
5	IO1	bidirectional	Input/output 1 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
6	IO2	bidirectional	Input/output 2 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
7	IO3	bidirectional	Input/output 3 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
8	VSS	power_in	Supply ground; it must be connected to the supply ground for proper device operation.
9	IO4	bidirectional	Input/output 4 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
10	IO5	bidirectional	Input/output 5 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
11	IO6	bidirectional	Input/output 6 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
12	IO7	bidirectional	Input/output 7 is a general-purpose I/O that defaults to an input at reset and can be raised above VDD up to a maximum of 5.5 V when configured as an input.
13	INT	output	Open-drain active LOW interrupt output that is activated when any input state differs from its Input Port register state.
14	SCL	input	Serial clock line for the I2C-bus/SMBus interface, supporting 0 Hz to 400 kHz clock frequency with a noise filter on its input.
15	SDA	bidirectional	Serial data line for the I2C-bus/SMBus interface, with a noise filter on its input.
16	VDD	power_in	Supply voltage with an operating range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9538PW/Q900).

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	TSSOP-16
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	-0.5		6	V		14
Input current	II	-20		20	mA		14
Voltage on an input/output pin	VI/O			5.5	V	min printed as VSS - 0.5	14
Output current on pin IOn	IO(IOn)	-50		50	mA		14
Supply current	IDD			85	mA		14
Ground supply current	ISS			100	mA		14
Total power dissipation	Ptot			200	mW		14
Storage temperature	Tstg	-65		150	°C		14
Ambient temperature, operating	Tamb	-40		85	°C	All devices except PCA9538PW/Q900	14
Maximum junction temperature	Tj(max)			125	°C		14
Supply voltage	VDD	2.3		5.5	V		15
Supply current	IDD		104	175	μA	Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz	15
LOW-level standby current	IstbL		0.25	1	μA	Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs	15
HIGH-level standby current	IstbH		0.25	1	μA	Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs	15
Power-on reset voltage	VPOR		1.7	2.2	V	No load; VI = VDD or VSS	15
LOW-level input voltage, SCL and SDA	VIL	-0.5			V	Input SCL; input/output SDA; upper limit +0.3VDD	15
HIGH-level input voltage, SCL and SDA	VIH			5.5	V	Input SCL; input/output SDA; lower limit 0.7VDD	15
LOW-level output current, SDA	IOL	3	7		mA	VOL = 0.4 V	15
Leakage current, SCL	IL	-1		1	μA	VI = VDD = VSS	15
Input capacitance, SCL	Ci		5	10	pF	VI = VSS	15
LOW-level input voltage, I/Os	VIL	-0.5			V	I/Os; upper limit +0.3VDD	15
HIGH-level input voltage, I/Os	VIH			5.5	V	I/Os; lower limit 0.7VDD	15
LOW-level output current, I/Os	IOL	8	10		mA	VOL = 0.5 V; VDD = 2.3 V	15
LOW-level output current, I/Os	IOL	8	14		mA	VOL = 0.5 V; VDD = 3.0 V	15
LOW-level output current, I/Os	IOL	8	17		mA	VOL = 0.5 V; VDD = 4.5 V	15
LOW-level output current, I/Os	IOL	10	13		mA	VOL = 0.7 V; VDD = 2.3 V	15
LOW-level output current, I/Os	IOL	10	19		mA	VOL = 0.7 V; VDD = 3.0 V	15
LOW-level output current, I/Os	IOL	10	24		mA	VOL = 0.7 V; VDD = 4.5 V	15
HIGH-level output voltage, I/Os	VOH	1.8			V	IOH = -8 mA; VDD = 2.3 V	15
HIGH-level output voltage, I/Os	VOH	2.6			V	IOH = -8 mA; VDD = 3.0 V	15
HIGH-level output voltage, I/Os	VOH	4.1			V	IOH = -8 mA; VDD = 4.5 V	15
HIGH-level output voltage, I/Os	VOH	1.7			V	IOH = -10 mA; VDD = 2.3 V	15
HIGH-level output voltage, I/Os	VOH	2.5			V	IOH = -10 mA; VDD = 3.0 V	16
HIGH-level output voltage, I/Os	VOH	4			V	IOH = -10 mA; VDD = 4.5 V	16
Input leakage current, I/Os	ILI	-1		1	μA	VI = VDD = VSS	16
Input capacitance, I/Os	Ci		5	10	pF		16
LOW-level output current, INT	IOL	3	13		mA	VOL = 0.4 V	16
LOW-level input voltage, A0, A1, RESET	VIL	-0.5		0.8	V		16
HIGH-level input voltage, A0, A1, RESET	VIH	2		5.5	V		16
Input leakage current, A0, A1, RESET	ILI	-1		1	μA		16
SCL clock frequency	fSCL	0		100	kHz	Standard-mode I2C-bus	18
SCL clock frequency	fSCL	0		400	kHz	Fast-mode I2C-bus	18
Bus free time between a STOP and START condition	tBUF	4.7			μs	Standard-mode I2C-bus	18
Bus free time between a STOP and START condition	tBUF	1.3			μs	Fast-mode I2C-bus	18
Rise time of both SDA and SCL signals	tr			1000	ns	Standard-mode I2C-bus	18
Rise time of both SDA and SCL signals	tr			300	ns	Fast-mode I2C-bus; lower limit 20+0.1Cb	18
Fall time of both SDA and SCL signals	tf			300	ns	Standard-mode I2C-bus	18
Data set-up time	tSU;DAT	250			ns	Standard-mode I2C-bus	18
Data set-up time	tSU;DAT	100			ns	Fast-mode I2C-bus	18
Pulse width of spikes that must be suppressed by the input filter	tSP			50	ns	Standard-mode I2C-bus	18
Data output valid time	tv(Q)			200	ns	Port timing	18
Data input set-up time	tsu(D)	100			ns	Port timing	18
Data input hold time	th(D)	1			μs	Port timing	18
Reset pulse width	tw(rst)	4			ns	RESET	18
Reset time	trst	400			ns	RESET	18

CAD (KiCad official)

Symbol: PCA9538PW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: pca9538pw-etched.step / pca9538pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pca9538pw.step / pca9538pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (37 pp, sha256 fcc5a3c0acdca85d, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

PCA9538PW

Verified PCA9538PW

Verification log 1 record

3D Model

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Schematic Symbol

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Datasheet

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