PCA9513ADP from NXP Semicon, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ENABLE	input	Chip enable; grounding this input puts the part in a low current (< 1 µA) mode and also disables the rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT.
2	SCLOUT	bidirectional	Serial clock output to and from the SCL bus on the card.
3	SCLIN	bidirectional	Serial clock input to and from the SCL bus on the backplane; on the PCA9513A this pin has the 92 µA pull-up current source.
4	GND	power_in	Ground; connect this pin to a ground plane for best results.
5	READY	output	Open-drain output that pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT and SCLOUT and goes HIGH when the two sides are connected.
6	SDAIN	bidirectional	Serial data input to and from the SDA bus on the backplane; on the PCA9513A this pin has the 92 µA pull-up current source.
7	SDAOUT	bidirectional	Serial data output to and from the SDA bus on the card.
8	VCC	power_in	Power supply; the operating range is 2.7 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	NXP Semicon
Package	TSSOP-8
Category	Logic ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating temperature	Toper	-40		85	°C		14
Supply voltage (absolute maximum, with respect to GND)	VCC	-0.5		7	V	Voltages with respect to pin GND	14
Voltage on any other pin (absolute maximum, with respect to GND)	Vn	-0.5		7	V	Voltages with respect to pin GND	14
Storage temperature	Tstg	-65		150	°C		14
Solder point temperature	Tsp			300	°C	10 s max.	14
Maximum junction temperature	Tj(max)			125	°C		14
Supply voltage	VCC	2.7		5.5	V		14
Supply current	ICC		3.5	6	mA	VCC = 5.5 V; VSDAIN = VSCLIN = 0 V	14
HIGH-level input voltage on pin ENABLE (printed as multiple of VCC)	VIH(ENABLE)		0.5	0.7	× VCC		14
LOW-level input voltage on pin ENABLE (printed as multiple of VCC)	VIL(ENABLE)	0.3	0.5		× VCC		14
Input current on pin ENABLE	II(ENABLE)	-1		1	µA	VENABLE = 0 V to VCC	14
Off-state leakage current on pin READY	ILZ(READY)	-0.3		0.3	µA	VENABLE = VCC	14
Input capacitance on pin ENABLE	Ci(ENABLE)		1.9	4	pF	VI = VCC or GND	14
Output capacitance on pin READY	Co(READY)		2.5	4	pF	VI = VCC or GND	14
LOW-level output voltage on pin READY	VOL(READY)		0.04	0.4	V	Ipu = 3 mA; VENABLE = VCC	14
Transient boosted pull-up current	Itrt(pu)	1	2		mA	positive transition on SDA, SCL; VCC = 2.7 V; slew rate = 1.25 V/µs	15
Offset voltage	Voffset	0	118	175	mV	10 kΩ to VCC on SDA, SCL; VCC = 3.3 V	15
SCL and SDA input capacitance	Ci(SCL/SDA)		6	8	pF		15
LOW-level output voltage on SDAn, SCLn pins	VOL	0	0.3	0.4	V	VI = 0 V; SDAn, SCLn pins; Isink = 3 mA; VCC = 2.7 V	15
Pull-up current on pin SCLIN (PCA9513A only)	Ipu(SCLIN)	65	112	150	µA	VENABLE = VCC; PCA9513A only	15
Pull-up current on pin SDAIN (PCA9513A only)	Ipu(SDAIN)	65	112	150	µA	VENABLE = VCC; PCA9513A only	15
Input leakage current on SDAn, SCLn pins	ILI	-1		1	µA	SDAn, SCLn pins; VCC = 5.5 V	15
SCL clock frequency	fSCL	0		400	kHz		15
Bus free time between STOP and START condition	tBUF	1.3			µs		15
Hold time (repeated) START condition	tHD;STA	0.6			µs		15
Set-up time for a repeated START condition	tSU;STA	0.6			µs		15
Set-up time for STOP condition	tSU;STO	0.6			µs		15
Data hold time	tHD;DAT	300			ns		15
Data set-up time	tSU;DAT	100			ns		15
LOW period of the SCL clock	tLOW	1.3			µs		15
HIGH period of the SCL clock	tHIGH	0.6			µs		15
Fall time of both SDA and SCL signals	tf	20		300	ns	min expression is 20 + 0.1 × Cb (Cb in pF)	15
Rise time of both SDA and SCL signals	tr	20		300	ns	min expression is 20 + 0.1 × Cb (Cb in pF)	15
Shut-down mode supply current	ICC(sd)		16		µA	VENABLE = 0 V; all other pins at VCC or GND	14
Enable time	ten		110		µs		14
Disable time (ENABLE to READY)	tdis(EN-RDY)		30		ns		14
SDAIN to READY delay after STOP	tstp(READY)		1.3		µs		14
SCLOUT/SDAOUT to READY delay	tREADY		0.8		µs		14
LOW to HIGH propagation delay	tPLH		20		ns	SCL to SCL and SDA to SDA; 10 kΩ to VCC; CL = 100 pF each side	15
HIGH to LOW propagation delay	tPHL		80		ns	SCL to SCL and SDA to SDA; 10 kΩ to VCC; CL = 100 pF each side	15

CAD (KiCad official)

Symbol: PCA9513ADP
Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
3D model: TSSOP-8 (KiCad packages3D, STEP)
3D model files: pca9513adp-etched.step / pca9513adp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pca9513adp.step / pca9513adp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: NXP Semicon datasheet (26 pp, sha256 bc7812437c1c61f1, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

PCA9513ADP

Verified PCA9513ADP

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README