component

PCA9306TDCURQ1

Public Made by Adom

by adom

Texas Instruments Translators / Level Shifters, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icspca9306tdcurq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

PCA9306TDCURQ1

Texas Instruments · Translators / Level Shifters · VSSOP-8

PCA9306TDCURQ1 from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground, 0 V.
2 VREF1 power_in Low-voltage-side reference supply voltage for SCL1 and SDA1; recommended operating range 0 to 5 V.
3 SCL1 bidirectional Serial clock, low-voltage side, open-drain I/O connected to VREF1 through a pullup resistor; recommended I/O voltage 0 to 5 V.
4 SDA1 bidirectional Serial data, low-voltage side, open-drain I/O connected to VREF1 through a pullup resistor; recommended I/O voltage 0 to 5 V.
5 SDA2 bidirectional Serial data, high-voltage side, open-drain I/O connected to VREF2 through a pullup resistor; recommended I/O voltage 0 to 5 V.
6 SCL2 bidirectional Serial clock, high-voltage side, open-drain I/O connected to VREF2 through a pullup resistor; recommended I/O voltage 0 to 5 V.
7 VREF2 power_in High-voltage-side reference supply voltage for SCL2 and SDA2; recommended operating range 0 to 5 V.
8 EN input Switch enable input, connected to VREF2 and pulled up through a high resistor; recommended input voltage 0 to 5 V, and a low level makes SCL/SDA pins high-impedance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-8
Category Logic ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VREF1 DC reference voltage VREF1 -0.5 7 V 5
VREF2 DC reference bias voltage VREF2 -0.5 7 V 5
Input voltage VI -0.5 7 V 5
Input/output voltage VI/O -0.5 7 V 5
Continuous channel current 128 mA 5
Input clamp current IIK -50 mA VI < 0 5
Storage temperature Tstg -65 150 °C 5
ESD HBM V(ESD) -2000 2000 V HBM, per AEC Q100-002 5
ESD CDM V(ESD) -750 750 V CDM, per AEC Q100-011 5
Input/output voltage SCL1, SDA1, SCL2, SDA2 VI/O 0 5 V 5
Reference voltage VREF1 VREF1 0 5 V 5
Reference voltage VREF2 VREF2 0 5 V 5
Enable input voltage EN 0 5 V 5
Pass switch current IPASS 64 mA 5
Operating free-air temperature TA -40 105 °C 5
Junction-to-ambient thermal resistance RθJA 275.5 °C/W DCU (VSSOP) 8 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 127.1 °C/W 5
Junction-to-board thermal resistance RθJB 186.9 °C/W 5
Junction-to-top characterization parameter ψJT 65.7 °C/W 5
Junction-to-board characterization parameter ψJB 185.9 °C/W 5
Input clamp voltage VIK -1.2 0 V II = -18 mA, EN = 0 V 6
Input leakage current IIH 5 μA VI = 5 V, EN = 0 V 6
Input capacitance EN Ci(EN) 11 pF VI = 3 V or 0 V 6
Off capacitance SCLn, SDAn Cio(off) 4 6 pF VO = 3 V or 0 V, EN = 0 V 6
On capacitance SCLn, SDAn Cio(on) 10.5 12.5 pF VO = 3 V or 0 V, EN = 3 V 6
ON-state resistance ron 3.5 5.5 Ω VI = 0 V, IO = 64 mA, EN = 4.5 V 6
ON-state resistance ron 4.7 7 Ω VI = 0 V, IO = 64 mA, EN = 3 V 6
ON-state resistance ron 6.3 9.5 Ω VI = 0 V, IO = 64 mA, EN = 2.3 V 6
ON-state resistance ron 25.5 32 Ω VI = 0 V, IO = 64 mA, EN = 1.5 V 6
ON-state resistance ron 1 6 15 Ω VI = 2.4 V, IO = 15 mA, EN = 4.5 V 6
ON-state resistance ron 20 60 140 Ω VI = 2.4 V, IO = 15 mA, EN = 3 V 6
Propagation delay tPLH down 3.3 V tPLH 0.8 ns SCL2/SDA2 to SCL1/SDA1, CL = 50 pF, EN = 3.3 V, VIH = 3.3 V 6
Propagation delay tPLH down 3.3 V tPLH 0.6 ns CL = 30 pF 6
Propagation delay tPLH down 3.3 V tPLH 0.3 ns CL = 15 pF 6
Propagation delay tPHL down 3.3 V tPHL 1.2 ns CL = 50 pF 6
Propagation delay tPHL down 3.3 V tPHL 1 ns CL = 30 pF 6
Propagation delay tPHL down 3.3 V tPHL 0.75 ns CL = 15 pF 6
Propagation delay tPLH down 2.5 V tPLH 1 ns CL = 50 pF, EN = 2.5 V, VIH = 2.5 V 6
Propagation delay tPLH down 2.5 V tPLH 0.7 ns CL = 30 pF 6
Propagation delay tPLH down 2.5 V tPLH 0.4 ns CL = 15 pF 6
Propagation delay tPHL down 2.5 V tPHL 1.3 ns CL = 50 pF 6
Propagation delay tPHL down 2.5 V tPHL 1 ns CL = 30 pF 6
Propagation delay tPHL down 2.5 V tPHL 0.75 ns CL = 15 pF 6
Propagation delay tPLH up 2.3 V tPLH 0.9 ns SCL1/SDA1 to SCL2/SDA2, CL = 50 pF, EN = 3.3 V, VIH = 2.3 V, RL = 300 Ω; specified by design 7
Propagation delay tPLH up 2.3 V tPLH 0.6 ns CL = 30 pF; specified by design 7
Propagation delay tPLH up 2.3 V tPLH 0.4 ns CL = 15 pF; specified by design 7
Propagation delay tPHL up 2.3 V tPHL 1.4 ns CL = 50 pF; specified by design 7
Propagation delay tPHL up 2.3 V tPHL 1.1 ns CL = 30 pF; specified by design 7
Propagation delay tPHL up 2.3 V tPHL 0.7 ns CL = 15 pF; specified by design 7
Propagation delay tPLH up 1.5 V tPLH 1 ns CL = 50 pF, EN = 2.5 V, VIH = 1.5 V, RL = 300 Ω; specified by design 7
Propagation delay tPLH up 1.5 V tPLH 0.6 ns CL = 30 pF; specified by design 7
Propagation delay tPLH up 1.5 V tPLH 0.4 ns CL = 15 pF; specified by design 7
Propagation delay tPHL up 1.5 V tPHL 1.3 ns CL = 50 pF; specified by design 7
Propagation delay tPHL up 1.5 V tPHL 0.8 ns CL = 15 pF; specified by design 7

CAD (KiCad official)

  • Symbol: PCA9306TDCURQ1
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: pca9306tdcurq1-etched.step / pca9306tdcurq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pca9306tdcurq1.step / pca9306tdcurq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 dec1cb1e56801f0e, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF