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PB7170

Public Made by Adom

by adom

PST Battery Management, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PB7170

PST · Battery Management · LQFP-64(10x10)

PB7170 from PST, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD power_in High-voltage DC supply positive input connected to the highest-voltage cell point; recommended supply 12-80 V, absolute maximum VPVDD-VPGND 88 V.
2 C17 input Positive connection pin for cell 17; recommended cell voltage VC17-VC16 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
3 S17 output Balancing switch control pin for cell 17; absolute range VS17-VC16 is -0.5 to 10 V, and balancing current is limited to 100 mA per cell (recommended).
4 C16 input Positive connection pin for cell 16; recommended cell voltage VC16-VC15 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
5 S16 output Balancing switch control pin for cell 16; absolute range VS16-VC15 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
6 C15 input Positive connection pin for cell 15; recommended cell voltage VC15-VC14 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
7 S15 output Balancing switch control pin for cell 15; absolute range VS15-VC14 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
8 C14 input Positive connection pin for cell 14; recommended cell voltage VC14-VC13 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
9 S14 output Balancing switch control pin for cell 14; absolute range VS14-VC13 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
10 C13 input Positive connection pin for cell 13; recommended cell voltage VC13-VC12 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
11 S13 output Balancing switch control pin for cell 13; absolute range VS13-VC12 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
12 C12 input Positive connection pin for cell 12; recommended cell voltage VC12-VC11 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
13 S12 output Balancing switch control pin for cell 12; absolute range VS12-VC11 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
14 C11 input Positive connection pin for cell 11; recommended cell voltage VC11-VC10 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
15 S11 output Balancing switch control pin for cell 11; absolute range VS11-VC10 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
16 C10 input Positive connection pin for cell 10; recommended cell voltage VC10-VC9 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
17 S10 output Balancing switch control pin for cell 10; absolute range VS10-VC9 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
18 C9 input Positive connection pin for cell 9; recommended cell voltage VC9-VC8 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
19 S9 output Balancing switch control pin for cell 9; absolute range VS9-VC8 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
20 C8 input Positive connection pin for cell 8; recommended cell voltage VC8-VC7 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
21 S8 output Balancing switch control pin for cell 8; absolute range VS8-VC7 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
22 C7 input Positive connection pin for cell 7; recommended cell voltage VC7-VC6 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
23 S7 output Balancing switch control pin for cell 7; absolute range VS7-VC6 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
24 C6 input Positive connection pin for cell 6; recommended cell voltage VC6-VC5 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
25 S6 output Balancing switch control pin for cell 6; absolute range VS6-VC5 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
26 C5 input Positive connection pin for cell 5; recommended cell voltage VC5-VC4 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
27 S5 output Balancing switch control pin for cell 5; absolute range VS5-VC4 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
28 C4 input Positive connection pin for cell 4; recommended cell voltage VC4-VC3 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
29 S4 output Balancing switch control pin for cell 4; absolute range VS4-VC3 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
30 C3 input Positive connection pin for cell 3; recommended cell voltage VC3-VC2 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
31 S3 output Balancing switch control pin for cell 3; absolute range VS3-VC2 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
32 C2 input Positive connection pin for cell 2; recommended cell voltage VC2-VC1 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
33 S2 output Balancing switch control pin for cell 2; absolute range VS2-VC1 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
34 C1 input Positive connection pin for cell 1; recommended cell voltage VC1-VC0 is -0.5 to 5 V (absolute maximum -0.5 to 10 V).
35 S1 output Balancing switch control pin for cell 1; absolute range VS1-VC0 is -0.5 to 10 V, with 100 mA recommended balancing current per cell.
36 C0 input Lowest cell connection pin, printed in the datasheet pin table as the negative connection of cell 1; recommended cell voltage range applies as for other Cn pins.
37 PGND power_in High-voltage DC supply negative input connected to the lowest-voltage cell point and the reference ground for PVDD.
38 SRP input Positive end of the current-sense resistor; recommended differential VSRP-VSRN is -230 to 230 mV (absolute ±500 mV), and any series resistor to PGND should be kept below 1 kΩ.
39 SRN input Negative end of the current-sense resistor; recommended differential VSRP-VSRN is -230 to 230 mV (absolute ±500 mV), and any series resistor to PGND should be kept below 1 kΩ.
40 DSG output Discharge MOSFET gate drive; VMOS_ON is 8-13 V (10 V typical) and the absolute maximum is 20 V.
41 PREMOS output Pre-charge/pre-discharge MOSFET gate drive; VMOS_ON is 8-13 V (10 V typical) and the absolute maximum is 20 V.
42 CHG output Charge MOSFET gate drive; VMOS_ON is 8-13 V (10 V typical) and the absolute maximum is 20 V.
43 LODD input Load detection input with a detection threshold of 1 to 1.7 V and an internal 100 kΩ pull-down; absolute range is -0.5 to 5.5 V.
44 CHGD input Charger detection input with a detection voltage of -950 to -500 mV and an internal 100 kΩ pull-down; absolute range is -0.5 to 5.5 V.
45 AGND power_in Internal analog ground, connected at a single point near PGND (pin 37).
46 VREF power_in ADC reference voltage output that requires a decoupling capacitor to AGND placed close to the pin (100 nF recommended).
47 AVDD power_out Analog supply output (5 V typical) that requires a decoupling capacitor to AGND placed close to the pin (100 nF recommended).
48 VAA power_out External measurement supply output (5 V typical) that can power the thermistor divider network; a 10 nF port capacitor is recommended for a 10 kΩ NTC.
49 AUXIN4 input Auxiliary measurement input 4 for a temperature or other sensor analog output; recommended range 0.5-4.5 V, absolute range -0.5 to 5.5 V.
50 AUXIN3 input Auxiliary measurement input 3 for a temperature or other sensor analog output; recommended range 0.5-4.5 V, absolute range -0.5 to 5.5 V.
51 AUXIN2 input Auxiliary measurement input 2 for a temperature or other sensor analog output; recommended range 0.5-4.5 V, absolute range -0.5 to 5.5 V.
52 AUXIN1 input Auxiliary measurement input 1 for a temperature or other sensor analog output; recommended range 0.5-4.5 V, absolute range -0.5 to 5.5 V.
53 DRIVE output Drive output for an external NPN linear regulator, selectable at 4 V (default) or 5.7 V, with a 1 nF output capacitor and output current kept within 10 mA; the datasheet specifies a 30 mA maximum at PVDD=12 V.
54 ACT input High-level activation pin with an internal 8 MΩ pull-up; pulling it low enters shutdown mode, and activation requires 2.5-5 V (shutdown at 0-0.6 V).
55 DVDD power_out Digital supply output (3.3 V) that requires a decoupling capacitor to DGND placed close to the pin.
56 ALERT bidirectional Open-drain interrupt output, active low, that also acts as an external protection input (forcing it low triggers protection); an external pull-up is required, with input high 2.5-3.6 V and output low max 0.6 V.
57 PROG input Configuration pin to be connected to DGND, with input low max 0.6 V and input high 2-4 V.
58 GPIO1 bidirectional General-purpose input/output 1 with output high 2.8-3.6 V, output low max 0.4 V, and 16 mA source/sink capability; default is floating.
59 GPIO0 bidirectional General-purpose input/output 0 with output high 2.8-3.6 V, output low max 0.4 V, and 16 mA source/sink capability; default is floating.
60 SDO output SPI slave data output that is driven low when CSN is high and the device is not asleep, and requires an external pull-down resistor.
61 SDI input SPI slave data input with input low max 0.6 V and input high 2-4 V.
62 CSN input Active-low SPI chip select; a low level during sleep wakes the device (1 ms before access in deep sleep, 250 µs in light sleep).
63 SCLK input SPI slave clock input with a minimum clock period of 500 ns.
64 DGND power_in Digital ground, connected at a single point near PGND (pin 37).

Key specifications

Parameter Value
Manufacturer PST
Package LQFP-64(10x10)
Category Power Management (PMIC)
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage PVDD to PGND VPVDD-VPGND -0.5 88 V 9
Cell pin voltage CN VCn, VCn-1 -0.5 10 V n=1-17 9
Balance switch pin voltage SN VSn, VCn-1 -0.5 10 V n=1-17 9
AUXIN input voltage VAUXIN, VAGND -0.5 5.5 V 10
Current sense voltage VSRP, VSRN -500 500 mV 10
MOS drive output -0.5 20 V CHG, DSG, PREMOS 10
DRIVE output -0.5 10 V 10
Digital signal pins -0.5 5.5 V CSN, SDI, SDO, SCLK, ALERT, GPIO0, GPIO1, PROG 10
Other ports -0.5 5.5 V DVDD, AVDD, ACT, VAA, VREF, CHGD, LODD, SPR, SRN (SPR as printed) 10
Operating temperature -40 125 °C 10
Storage temperature -65 150 °C 10
Total supply voltage VPVDD-VPGND 12 80 V 10
Cell voltage VCn, VCn-1 -0.5 5 V n=1-17 10
AUXIN input voltage VAUXIN, VAGND 0.5 4.5 V 10
Current input VSRP, VSRN -230 230 mV 10
MOS drive output 0 13 V CHG, DSG, PREMOS 10
DRIVE output 0 V Configurable 4V/5.7V; max printed as 4/5.7 10
Digital signal input 0 3.6 V CSN, SDI, SCLK, ALERT 10
Digital signal output 0 3.6 V SDO, GPIO0, GPIO1, ALERT 10
Operating temperature -20 85 °C 10
VADC voltage measurement range VRANGE -0.5 5 V 11
VADC voltage measurement accuracy ACC1 -2 2 mV TA=25°C Vcell=3.6V 11
VADC voltage measurement accuracy ACC1 -5 5 mV -20~85°C 11
VADC voltage measurement accuracy ACC1 -10 10 mV -40~125°C 11
VADC single-channel sampling time TVADC 128 512 4096 时钟周期 通过 VADC_MSR [2:0] 配置 11
VADC fast current measurement range CRANGE -300 300 mV 11
VADC fast current measurement accuracy CACC -1 1 mV 11
CADC current integration range RANGECC -250 250 mV 11
CADC integral nonlinearity error CCINL -1 1 LSB 11
MOS drive voltage VMOS_ON 8 10 13 V CHG, DSG, PREMOS 12
Overvoltage protection threshold VOV 0 4.2 6.5 V 通过寄存器 THR_OVSET [12:0]配置 12
Overvoltage protection delay count NOV 1 1 8 次 通过寄存器 DLY_OVUV [11:9]配置 12
Overvoltage recovery threshold VOVR 0 4.3 6.5 V 通过寄存器 THR_OVCLR [12:0]配置 12
Undervoltage protection threshold VUV 0 2.8 6.5 V 通过寄存器 THR_UVSET [12:0]配置 12
Undervoltage protection delay count NUV 1 1 8 次 通过寄存器 DLY_OVUV [5:3]配置 12
Undervoltage recovery threshold VUVR 0 2.9 6.5 V 通过寄存器 THR_UVCLR[12:0]配置 12
Discharge overcurrent protection threshold VOCD 10 10 200 mV 通过寄存器 THR_CD[4:0]配置 12
Discharge overcurrent protection delay TOCD 10 10 1280 mS 通过寄存器 PROT_CTRL [10:7]配置 12
Discharge short-circuit protection threshold VSCD 20 20 400 mV 通过寄存器 THR_CD [9:5]配置 12
Discharge short-circuit protection delay TSCD 0 0 448 μS 通过寄存器 PROT_CTRL [6:3]配置 12
Charge overcurrent protection threshold VOCC 10 10 200 mV 通过寄存器 THR_CD [14:10]配置 12
Charge overcurrent protection delay TOCC 10 10 1280 mS 通过寄存器 PROT_CTRL [2:0]配置 12
Low-voltage charge inhibit threshold VLV 1.64 2.5 3.25 V 通过寄存器 THR_LV 配置 13
ALERT output high VALERT_OH 2.5 3.3 V ALERT 外部上拉 13
ALERT output low VALERT_OL 0 0 0.6 V IOL = 1mA, ALERT 外部上拉，建议放置 4.7K 外部上拉电阻 13
ALERT input high VALERT_IH 2.5 3.6 V 13
ALERT input low VALERT_IL -0.3 0.6 V ALERT 外部下拉 13
CHGD detection voltage VCHGD -950 -500 mV CHG 断开 13
LODD detection voltage VLODD 1 1.7 V DSG 断开 13
Balance on-time TBL 0.25 1020 S 通过 BLSW_CMD 配置 13
Balance duty cycle XBL 12.5 12.5 100 % PWM 周期为 250mS 占空比用 BLSW_PWM_DUTY 调节 13
Activation voltage (shutdown to standby) VACT 2.5 3.3 5 V ACT 对 AGND 关机模式切换到待机模式 13
Shutdown voltage (standby to shutdown) VSD 0 0 0.6 V ACT 对 AGND 待机模式切换到关机模式 13
Wake-up time (deep sleep) Twakup 0.9 1 1.1 mS 深睡 DEEP = 1 睡眠模式切换到待机模式 13
Wake-up time (shallow sleep) Twakup 180 200 250 μS DEEP = 0 睡眠模式切换到待机模式 14
Digital input low VIL -0.3 0 0.6 V CSN, SCLK, SDI, ALERT, PROG 14
Digital input high VIH 2 3.3 4 V CSN, SCLK, SDI, ALERT, PROG 14
Digital output low VOL -0.3 0 0.4 V GPIO0, GPIO1, SDO, ALERT 14
Digital output high VOH 2.8 3.3 3.6 V GPIO0, GPIO1, SDO, ALERT 14
Shutdown mode supply current IPVDD 2 μA ACT 引脚拉低 10

CAD (KiCad official)

  • Symbol: PB7170
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pb7170-etched.step / pb7170-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pb7170.step / pb7170.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PST datasheet (29 pp, sha256 6525ab4196957633, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF