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PB7130

Public Made by Adom

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PST Battery Management ICs, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PB7130

PST · Battery Management ICs · LQFP-64(10x10)

PB7130 from PST, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD power_in High-voltage DC supply positive input, connected to the highest-voltage point of the measured cell stack; total supply 12-81 V per section 7.2.
2 C13 input Positive connection of cell 13; cell voltage range VCn-VCn-1 is -0.5 to 5 V (recommended).
3 S13 output Discharge (balancing) switch port for cell 13; external balancing pin with internal balance current up to 100 mA.
4 C12 input Positive connection of cell 12 and negative connection of cell 13.
5 S12 output Discharge (balancing) switch port for cell 12.
6 C11 input Positive connection of cell 11 and negative connection of cell 12.
7 S11 output Discharge (balancing) switch port for cell 11.
8 C10 input Positive connection of cell 10 and negative connection of cell 11.
9 S10 output Discharge (balancing) switch port for cell 10.
10 C9 input Positive connection of cell 9 and negative connection of cell 10.
11 S9 output Discharge (balancing) switch port for cell 9.
12 C8 input Positive connection of cell 8 and negative connection of cell 9.
13 S8 output Discharge (balancing) switch port for cell 8.
14 C7 input Positive connection of cell 7 and negative connection of cell 8.
15 S7 output Discharge (balancing) switch port for cell 7.
16 C6 input Positive connection of cell 6 and negative connection of cell 7.
17 S6 output Discharge (balancing) switch port for cell 6.
18 C5 input Positive connection of cell 5 and negative connection of cell 6.
19 S5 output Discharge (balancing) switch port for cell 5.
20 C4 input Positive connection of cell 4 and negative connection of cell 5.
21 S4 output Discharge (balancing) switch port for cell 4.
22 C3 input Positive connection of cell 3 and negative connection of cell 4.
23 S3 output Discharge (balancing) switch port for cell 3.
24 C2 input Positive connection of cell 2 and negative connection of cell 3.
25 S2 output Discharge (balancing) switch port for cell 2.
26 C1 input Positive connection of cell 1 and negative connection of cell 2.
27 S1 output Discharge (balancing) switch port for cell 1.
28 C0 input Negative connection of cell 1 (bottom of the stack).
29 PGND power_in High-voltage DC supply negative input, connected to the lowest-voltage point of the measured cells.
30 SRP input Positive end of the current-sense resistor (connect to PGND); differential current range VSRP-VSRN is -230 to 230 mV recommended.
31 SRN input Negative end of the current-sense resistor.
32 DSG output Discharge MOSFET gate drive; MOS drive voltage 8-13 V (typ. 10 V).
33 PDSG output Pre-discharge MOSFET gate drive; MOS drive voltage 8-13 V (typ. 10 V).
34 PCHG output Pre-charge MOSFET gate drive; MOS drive voltage 8-13 V (typ. 10 V).
35 CHG output Charge MOSFET gate drive; MOS drive voltage 8-13 V (typ. 10 V).
36 CHGD input External charger detection input; detection voltage VCHGD is -950 to -500 mV with CHG off.
37 LODD input Load detection input; detection voltage VLODD is 1 to 1.7 V with DSG off.
38 AGND power_in Internal analog ground.
39 VREF power_out Reference voltage output; only a 100 nF decoupling capacitor to AGND is connected.
40 DSY_BASE output Tie to DVDD to set BASE, or to PGND to set STACK; used only in daisy-chain mode.
41 AVDD power_out Analog supply output (5 V typ.); only a 100 nF decoupling capacitor to AGND is connected.
42 NC unconnected Floating, do not connect.
43 DRIVE power_out External linear regulator drive, Vbe + 3.3 V output; drives an external NPN to give 3.3 V/5 V at the emitter (DRIVE voltage 4 V or 5.7 V configurable).
44 ACT input Chip activation pin, active high with an external capacitor to GND and an internal 8 MΩ pull-up; pulling it low enters the ultra-low-power shipping mode.
45 NC unconnected No connect.
46 NC unconnected No connect.
47 GPIO8 bidirectional General-purpose input/output 8; can be multiplexed as external temperature-sensor or external voltage-measurement input.
48 GPIO7 bidirectional General-purpose input/output 7; can be multiplexed as external temperature-sensor or external voltage-measurement input.
49 GND power_in Ground.
50 GPIO6 bidirectional General-purpose input/output 6; can be multiplexed as external temperature-sensor or external voltage-measurement input.
51 GPIO5 bidirectional General-purpose input/output 5; can be multiplexed as external temperature-sensor or external voltage-measurement input.
52 GPIO4 bidirectional General-purpose input/output 4; can be multiplexed as external temperature-sensor or external voltage-measurement input.
53 GPIO3 bidirectional General-purpose input/output 3; can be multiplexed as external temperature-sensor or external voltage-measurement input.
54 GPIO2 bidirectional General-purpose input/output 2; can be multiplexed as external temperature-sensor or external voltage-measurement input.
55 GPIO1 bidirectional General-purpose input/output 1; can be multiplexed as external temperature-sensor or external voltage-measurement input.
56 VTS power_out External measurement supply output (3.3 V) for the thermistor divider network.
57 DVDD power_out Digital supply output (3.3 V); requires a 4.7 µF decoupling capacitor to DGND.
58 ALERT output Interrupt alarm output; open-drain with no internal pull-up, compatible with external protection input.
59 PROG passive Reserved chip pin; recommended to be pulled to DGND through a pull-down resistor.
60 COMU3 output In SPI direct mode, the AFE serial data output SDO; in daisy-chain mode, LUART_N of STACK or L_RXD of BASE.
61 COMU2 input In SPI direct mode, the AFE serial data input SDI; in daisy-chain mode, LUART_P of STACK or L_TXD of BASE.
62 COMU1 input In SPI direct mode, the chip-select input CSN; in daisy-chain mode, HUART_N.
63 COMU0 input In SPI direct mode, the clock input SCLK; in daisy-chain mode, HUART_P.
64 DGND power_in Digital ground.

Key specifications

Parameter Value
Manufacturer PST
Package LQFP-64(10x10)
Category Power Management ICs
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
PVDD supply voltage VPVDD-VPGND -0.5 81 V 10
Cell voltage VCn-VCn-1 -0.5 10 V n=1-13 10
Cell discharge switch voltage VSn-VCn-1 -0.5 10 V n=1-13 10
AUXIN input voltage VAUXIN-VAGND -0.5 5.5 V 10
Current sense voltage VSRP-VSRN -500 500 mV 10
MOS drive output CHG, DSG, PCHG, PDSG -0.5 20 V 10
DRIVE output DRIVE -0.5 10 V 10
Digital signal pins CSN, SDI, SDO, SCLK, ALERT, GPIO1~GPIO10, PROG -0.5 5.5 V 10
Other ports DVDD, AVDD, ACT, VTS, VREF, SRP, SRN, DSY_BASE -0.5 5.5 V 10
Analog detect ports CHGD, LODD -0.5 81 V 10
Internal balance current 150 mA 单个 CELL 10
Operating temperature -40 125 °C 10
Storage temperature -65 150 °C 10
Soldering temperature 300 °C 持续时间 10S 10
ESD HBM 2 kV 10
ESD CDM 500 V 10
Total supply voltage VPVDD-VPGND 12 81 V 10
Cell unit voltage VCn-VCn-1 -0.5 5 V n=1-13 10
AUXIN input voltage VAUXIN-VAGND 0.5 3.3 V 10
Current input VSRP-VSRN -230 230 mV 10
MOS drive output CHG, DSG, PCHG, PDSG 0 13 V 10
DRIVE output DRIVE 0 4 V 可配置 4V 10
Digital signal input CSN, SDI, SCLK, ALERT 0 3.6 V 10
Digital signal output SDO, GPIOn, ALERT 0 3.6 V 10
Internal balance current 100 mA 单个 CELL 10
Operating temperature -20 85 °C 10
VADC measurement range VRANGE -0.3 5 V 测量范围 11
VADC measurement accuracy VACC1 -2 2 mV TA=25°C Vcell=3.6V 11
VADC measurement accuracy VACC1 -5 5 mV -20~85°C 11
VADC measurement accuracy VACC1 -10 10 mV -40~125°C 11
VADC fast current measurement range CRANGE -300 300 mV 测量范围 11
VADC fast current measurement accuracy CACC -1 1 mV 11
CADC measurement range RANGECC -250 250 mV 配置 ADC_MSR [2:1]=0 11
CADC measurement range RANGECC -125 125 mV 配置 ADC_MSR [2:1]=1 11
CADC measurement range RANGECC -62.5 62.5 mV 配置 ADC_MSR [2:1]=2 11
CADC integral nonlinearity error CCINL -2 2 LSB 11
MOS drive voltage VMOS_ON 8 10 13 V CHG, DSG, PDSG, PCHG 12
Overvoltage protection threshold VOV 0 4.2 5 V 配置 THR_OVSET [9:0] 12
Overvoltage recovery threshold hysteresis VOVR 0 0.2 4 V 配置 HYS_OV [7:0]配置过压保护迟滞 12
Overvoltage protection delay count NOV 1 3 15 次 配置 PRT_DLY_OV [2:0] 12
Overvoltage recovery delay count NOVR 1 3 15 次 配置 REC_DLY_OV [2:0] 12
Undervoltage protection threshold VUV 0 2.8 5 V 配置 THR_UV_SET [9:0] 12
Undervoltage recovery threshold hysteresis VUVR 0 0.2 4 V 配置 HYS_UV [7:0]配置欠压保护迟滞 12
Undervoltage protection delay count NUV 1 3 15 次 配置 PRT_DLY_UV [2:0] 12
Undervoltage recovery delay count NOVR 1 3 15 次 配置 REC_DLY_UV [2:0] 12
Discharge overcurrent threshold 1 VOCD1 4 28 128 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL3[14:10] 13
Discharge overcurrent threshold 2 VOCD2 10 80 200 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL3[9:5] 13
Discharge overcurrent threshold 3 VOCD3 10 100 200 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL3[4:0] 13
Discharge overcurrent threshold 1 (half) VOCD1 4 28 128 mV 配置 CUR_CTRL3[15]=1 配置 CUR_CTRL3[14:10] 13
Discharge overcurrent threshold 2 (half) VOCD2 5 40 100 mV 配置 CUR_CTRL3[15]=1 配置 CUR_CTRL3[9:5] 13
Discharge overcurrent threshold 3 (half) VOCD3 5 50 100 mV 配置 CUR_CTRL3[15]=1 配置 CUR_CTRL3[4:0] 13
Discharge overcurrent delay 1 TOCD1 250 1750 63750 mS 配置 DLY_OCD1[2:0] 13
Discharge overcurrent delay 2 TOCD2 10 40 1280 mS 配置 DLY_OCD2[2:0] 13
Discharge short-circuit threshold VSCD 20 200 400 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL2[4:0] 13
Short-circuit protection delay TSCD 0 256 1008 μS 配置 DLY_SCD [5:0] 13
Charge overcurrent threshold VOCC 10 40 200 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL2[9:5] 13
Charge overcurrent delay TOCC 10 40 1280 mS 配置 DLY_OCC [2:0] 13
Precharge current threshold IPCHG 0.25 1 1.6 mV 配置 CUR_CTRL3[15]=0 配置 CUR_CTRL2[15:10] 14
Precharge voltage threshold VPCHGD 0 0.8 1.6 V 配置 VOL_CTRL7[14:10] 14
Chip internal high temperature threshold TINTH 1000 1716.8 2612.8 mV 配置值*25.6+1000mV 14
Battery discharge high temperature threshold TOTD 0 0.7424 3.264 V 配置 THR_OTD [7:0] 15
ALERT output low VALERT_OL 0.6 V IOL = 1mA, ALERT 外部上拉 15
Digital input low level VIL 0.6 V CSN, SCLK, SDI,ALERT,PROG 16
Digital input high level VIH 2 4 V CSN, SCLK, SDI,ALERT,PROG 16

CAD (KiCad official)

  • Symbol: PB7130
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pb7130-etched.step / pb7130-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pb7130.step / pb7130.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PST datasheet (35 pp, sha256 6511c777b6371543, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF