main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 19d ago
viewers pam8965zla40-13: viewers · Ray 19d ago
package.json Publish 0.1.0 · Ray 19d ago
page.json Set visibility: public · Ray 19d ago
pam8965zla40-13-etched.glb Publish 0.1.0 · Ray 19d ago
pam8965zla40-13-etched.step pam8965zla40-13: factory component page (tier=lcsc) · Ray 19d ago
pam8965zla40-13-hero.glb pam8965zla40-13: hero GLB from the etched model (keeps the MPN mark) · Ray 19d ago
pam8965zla40-13-hero.overlay.json Publish 0.1.0 · Ray 19d ago
pam8965zla40-13.glb Publish 0.1.0 · Ray 19d ago
pam8965zla40-13.kicad_mod Publish 0.1.0 · Ray 19d ago
pam8965zla40-13.kicad_sym Publish 0.1.0 · Ray 19d ago
pam8965zla40-13.lbr Publish 0.1.0 · Ray 19d ago
pam8965zla40-13.step Publish 0.1.0 · Ray 19d ago
README.md Publish 0.1.0 · Ray 19d ago

PAM8965ZLA40-13

DIODES · Global Sourcing Parts · WQFN-40(5x5)

PAM8965ZLA40-13 from DIODES, in a WQFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FLT output Open-drain fault flag output that signals system faults including VBAT UVLO or OVLO, OTP, DC input, and audio SCP.
2 EN input Chip enable: High turns the device ON and Low turns it OFF, and this pin must not be left floating.
3 RINP input Right channel audio input, positive.
4 RINN input Right channel audio input, negative.
5 LINN input Left channel audio input, negative.
6 LINP input Left channel audio input, positive.
7 SSM input Spread spectrum modulation control: High = ON, Low = OFF, and this pin must not be left floating.
8 VDD power_out Internal 5V LDO output.
9 GND power_in Analog signal ground.
10 GND power_in Analog signal ground.
11 PLIM input Non-clip power limit setting; PLIM = VDD disables the power limit, and this pin must not be left floating.
12 PGND power_in Power ground for left channel.
13 LFBP input Left channel feedback positive; short to LOUTP and Kelvin connect to speaker for higher performance.
14 LOUTP output Left channel audio output, positive.
15 LBSTP power_in Left channel boot-strap supply for the high side, positive.
16 LPVDD power_in Left channel power supply for the Class-D H-bridge.
17 LBSTN power_in Left channel boot-strap supply for the high side, negative.
18 LOUTN output Left channel audio output, negative.
19 LFBN input Left channel feedback negative; short to LOUTN and Kelvin connect to speaker for higher performance.
20 PGND power_in Power ground for left channel.
21 GAIN input Audio channel gain setting: 4.5V or above = 26dB (maximum gain), 0.5V or below = 6dB (minimum gain), with each 100mV step being 0.5dB; this pin must not be left floating.
22 PGND power_in Power ground for boost converter.
23 PGND power_in Power ground for boost converter.
24 SW output Boost converter switching node.
25 SW output Boost converter switching node.
26 BST power_in Boost converter boot-strap supply.
27 PVDD power_out Boost converter output; connect this to pin 16 and pin 35.
28 PVDD power_out Boost converter output; connect this to pin 16 and pin 35.
29 VBAT2 power_in Battery supply input for the boost converter; see Application Information for decoupling requirements.
30 VBAT1 power_in Battery supply input for the system; see Application Information for decoupling requirements.
31 PGND power_in Power ground for right channel.
32 RFBN input Right channel feedback negative; short to ROUTN and Kelvin connect to speaker for higher performance.
33 ROUTN output Right channel audio output, negative.
34 RBSTN power_in Right channel boot-strap supply for the high side, negative.
35 RPVDD power_in Right channel power supply for the Class-D H-bridge.
36 RBSTP power_in Right channel boot-strap supply for the high side, positive.
37 ROUTP output Right channel audio output, positive.
38 RFBP input Right channel feedback positive; short to ROUTP and Kelvin connect to speaker for higher performance.
39 PGND power_in Power ground for right channel.
40 GND power_in Connect to system ground.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer DIODES
Package WQFN-40(5x5)
Category Global Sourcing Parts
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VBAT Supply Voltage (Pins VBAT1, VBAT2) VBAT -0.3 9 V 4
Audio Input Voltage VRINP, VRINN, VLINP, VLINN -0.3 5.5 V 4
Control Input Voltage VPLIM, VGAIN, VSSM -0.3 6 V 4
EN Control Input Voltage VEN -0.3 V 4
Boost Switching Voltage VSW -2 16 V within 10ns 4
Boost Switching Voltage VSW -0.3 10.2 V DC 4
Boost Output Voltage VPVDD, VLPVDD, VRPVDD -0.3 10.2 V DC 4
Class D Output Voltage VLOUTP, VLOUTN, VROUTP, VROUTN -1 12 V within 10ns 4
Class D Output Voltage VLOUTP, VLOUTN, VROUTP, VROUTN -1 10.2 V DC 4
Maximum Operating Junction Temperature TJ_MAX -40 150 °C 4
Storage Temperature Range TSTG -40 150 °C 4
HBM ESD (Human Body Model) -2000 2000 V 4
CDM ESD (Charged Device Model) -1000 1000 V 4
VBAT Supply Voltage (Pins VBAT1, VBAT2) VBAT 2.8 8.5 V 4
Audio Input Voltage VRINP, VRINN, VLINP, VLINN 0 5 V 4
Control Input Voltage VPLIM, VGAIN, VSSM 0 5.5 V 4
EN Control Input Voltage VEN 0 V 4
Minimum Load Resistance RLMIN 6 Ω VBAT ≤ 5.0V 4
Minimum Load Resistance 4 Ω VBAT > 5.0V 4
Operating Free-Air Temperature Range TA -40 85 °C 4
Operating Junction Temperature Range TJ -40 125 °C 4
VBAT Input Supply Voltage VBAT 2.8 8.5 V 5
High-Level Input Voltage (EN, SSM) VIH 1.5 V EN, SSM 5
Low-Level Input Voltage (EN, SSM) VIL 0.5 V EN, SSM 5
Shutdown Current ISD 0.7 5 μA VEN = 0, VBAT = 2.8V to 8.5V 5
VBAT UVLO Threshold (Falling) UVLO 2.3 2.45 2.55 V VBAT Falling 5
VBAT UVLO Threshold (Rising) UVLO 2.7 2.8 V VBAT Rising 5
VBAT OVLO Threshold (Rising) OVLO 8.6 8.95 9.2 V VBAT Rising 5
VBAT OVLO Threshold (Falling) OVLO 8.5 8.6 V VBAT Falling 5
Boost Switching Frequency in PFM 50 75 kHz No Load 5
Startup Time from EN Asserted tON 15 ms 6
Output Offset Voltage VOS 1 10 mV VIN @ AC Ground, Gain = 26dB 6
Thermal Resistance (Junction to Ambient) θJA 33 °C/W 4
Thermal Resistance (Junction to Case) θJC 10 °C/W 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: Finish, Matte Tin Plated Leads, Solderable per J-STD-002, Test B1 • Weight: 0.066 grams (Approximate) 24

CAD (KiCad official)

  • Symbol: PAM8965ZLA40-13
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: WQFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: pam8965zla40-13-etched.step / pam8965zla40-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pam8965zla40-13.step / pam8965zla40-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DIODES datasheet (25 pp, sha256 5536ddc83103e329, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF