# PAC5225QM

**Qorvo** · Motor Driver ICs · TQFN-48-EP(6x6)

PAC5225QM from Qorvo, in a TQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC4/AD4 | bidirectional | I/O port C4, or ADC input 4. |
| 2 | PC3/AD3 | bidirectional | I/O port C3, or ADC input 3. |
| 3 | PC2/AD2 | bidirectional | I/O port C2, or ADC input 2. |
| 4 | VCC33 | power_out | Internally generated 3.3V power supply; connect a 2.2μF or higher ceramic capacitor from VCC33 to VSSA. |
| 5 | AIO0/DA0N | bidirectional | Analog front end I/O 0, or differential PGA 0 negative input. |
| 6 | AIO1/DA0P/PCMP0 | bidirectional | Analog front end I/O 1, differential PGA 0 positive input, or protection comparator input 0. |
| 7 | AIO2/DA1N | bidirectional | Analog front end I/O 2, or differential PGA 1 negative input. |
| 8 | AIO3/DA1P/PCMP1 | bidirectional | Analog front end I/O 3, differential PGA 1 positive input, or protection comparator input 1. |
| 9 | AIO4/DA2N | bidirectional | Analog front end I/O 4, or differential PGA 2 negative input. |
| 10 | AIO5/DA2P/PCMP2 | bidirectional | Analog front end I/O 5, differential PGA 2 positive input, or protection comparator input 2. |
| 11 | AIO6/AMP6/CMP6/BUF6/PBTN | bidirectional | Analog front end I/O 6, PGA input 6, comparator input 6, buffer output 6, or push button input. |
| 12 | AIO7/AMP7/CMP7/PHC7 | bidirectional | Analog front end I/O 7, PGA input 7, comparator input 7, or phase comparator input 7. |
| 13 | AIO8/AMP8/CMP8/PHC8 | bidirectional | Analog front end I/O 8, PGA input 8, comparator input 8, or phase comparator input 8. |
| 14 | AIO9/AMP9/CMP9/PHC9 | bidirectional | Analog front end I/O 9, PGA input 9, comparator input 9, or phase comparator input 9. |
| 15 | VSYS | power_in | 5V system power supply; connect a 4.7μF or higher ceramic capacitor from VSYS to VSSP. |
| 16 | REGO | power_out | System regulator output; connect to VSYS directly or through an external power-dissipating resistor. |
| 17 | CSM | input | Switching supply current sense input; connect to the positive side of the current sense resistor. |
| 18 | VP | power_in | Main power supply for the power drivers and voltage feedback path of the switching supply; bypass to VSS with a bulk capacitor in parallel with a 0.1μF ceramic capacitor, with trace shorter than 10mm. |
| 19 | VHM | power_in | Switching supply controller supply input; bypass to VSSP with 1μF or higher ceramic (or 0.1μF ceramic plus 10μF or higher electrolytic), with trace shorter than 10mm. |
| 20 | DRM | output | Switching supply driver output; connect to the base or gate of the external power NPN or n-channel MOSFET. |
| 21 | DRL0 | output | Low-side gate driver 0. |
| 22 | DRL1 | output | Low-side gate driver 1. |
| 23 | DRL2 | output | Low-side gate driver 2. |
| 24 | DRS3 | passive | High-side gate driver source 3. |
| 25 | DRH3 | output | High-side gate driver 3. |
| 26 | DRB3 | passive | High-side gate driver bootstrap 3. |
| 27 | DRS4 | passive | High-side gate driver source 4. |
| 28 | DRH4 | output | High-side gate driver 4. |
| 29 | DRB4 | passive | High-side gate driver bootstrap 4. |
| 30 | DRS5 | passive | High-side gate driver source 5. |
| 31 | DRH5 | output | High-side gate driver 5. |
| 32 | DRB5 | passive | High-side gate driver bootstrap 5. |
| 33 | PA7/PWMA5/PWMA7/PWMC1/CLKOUT | bidirectional | I/O port A7, Timer A PWM/Capture 5 or 7, Timer C PWM/Capture 1, or low-speed clock output. |
| 34 | PD7/PWMA6/PWMD0 | bidirectional | I/O port D7, Timer A PWM/capture 6, or Timer D PWM/capture 0. |
| 35 | PD5/PWMA5/PWMC1 | bidirectional | I/O port D5, Timer A PWM/capture 5, or Timer C PWM/capture 1. |
| 36 | PD3/PWMA5/PWMA7/PWMB1 | bidirectional | I/O port D3, Timer A PWM/capture 5 or 7, or Timer B PWM/capture 1. |
| 37 | PD2/PWMA3/PWMA4/PWMB0 | bidirectional | I/O port D2, Timer A PWM/capture 3 or 4, or Timer B PWM/capture 0. |
| 38 | PD1/SWDCL/EXTCLK | bidirectional | I/O port D1, serial wire debug clock input, or external clock input. |
| 39 | PD0/SWDIO | bidirectional | I/O port D0, or serial wire debug I/O. |
| 40 | PE0/SPICLK | bidirectional | I/O port E0, or SPI clock. |
| 41 | PE1/SPIMOSI/UARTTX | bidirectional | I/O port E1, SPI master out slave in (MOSI), or UART transmit output. |
| 42 | PE2/SPIMISO/UARTRX | bidirectional | I/O port E2, SPI master in slave out (MISO), or UART receive input. |
| 43 | PE3/SPICS0/nRESET1 | bidirectional | I/O port E3, SPI chip select 0, or active-low reset input 1. |
| 44 | PE4/SPICS1/I2CSCL | bidirectional | I/O port E4, SPI chip select 1, or I2C clock. |
| 45 | PE5/SPICS2/I2CSDA | bidirectional | I/O port E5, SPI chip select 2, or I2C data. |
| 46 | VCCIO | power_out | Internally generated digital I/O power supply; connect a 4.7μF or higher ceramic capacitor from VCCIO to VSSA. |
| 47 | VSS | power_in | Ground. |
| 48 | VCC18 | power_out | Internally generated 1.8V core power supply; connect a 2.2μF or higher ceramic capacitor from VCC18 to VSSA. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Qorvo |
| Package | TQFN-48-EP(6x6) |
| Category | Power Management ICs |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VHM, DRM to VSSP |  | -0.3 |  | 72 | V |  | 11 |
| VP to VSS |  | -0.3 |  | 20 | V |  | 11 |
| VSYS, AIO6 to VSS |  | -0.3 |  | 6 | V |  | 11 |
| VCC33 to VSS |  | -0.3 |  | 4.1 | V |  | 11 |
| VCC18 to VSS |  | -0.3 |  | 2.5 | V |  | 11 |
| DRBx to VSSP |  | -0.3 |  | 84 | V |  | 11 |
| DRSx to VSSP |  | -6 |  | 72 | V |  | 11 |
| Operating temperature range |  | -40 |  | 105 | °C |  | 11 |
| ESD human body model |  |  |  | 2 | kV | JEDEC | 11 |
| VHM operating voltage range | VOP:VHM | 5 |  | 70 | V | VHM = 24V, VP = 12V | 25 |
| VHM UVLO rising | VUVLOR;VHM | 6.1 | 7.4 | 8 | V |  | 25 |
| VHM UVLO falling | VUVLOF;VHM | 5.1 | 6.6 | 7 | V |  | 25 |
| VP output regulation voltage | VREG;VP | -7 | -1 | 5 | % | Programmable to 5V, 9V, 12V, or 15V; Load = 0 to 500mA | 25 |
| Switching frequency accuracy | fSWMACC;DRM | -10 |  | 10 | % |  | 25 |
| VP operating voltage range | VOP;VP | 4.7 |  | 18 | V | VP = 12V | 27 |
| VP quiescent supply current | IQ;VP |  | 400 | 750 | µA | Power manager only, including IQ;VSYS | 27 |
| VSYS output voltage | VSYS | 4.8 | 5 | 5.18 | V | Load = 10µA to 200mA | 27 |
| VCCIO output voltage | VCCIO | 3.152 | 3.3 | 3.398 | V | Load = 10mA; VCCIO from regulator | 27 |
| VCC33 output voltage | VCC33 | 3.185 | 3.3 | 3.415 | V | Load = 10mA | 27 |
| VCC18 output voltage | VCC18 | 1.834 | 1.9 | 1.979 | V | Load = 10mA | 27 |
| Reference voltage | VREF | 2.463 | 2.5 | 2.537 | V | TA = -40°C to 105°C | 27 |
| Reference voltage at 25°C | VREF | 2.487 | 2.5 | 2.513 | V | TA = 25°C | 27 |
| Low-side gate driver low-level output voltage | VOL,DRL |  | 0.175 | 0.35 | V | IDRLx = 50mA | 46 |
| Trimmed RC oscillator frequency | fTRIM |  | 4 |  | MHz | TA = -40°C to 105°C, -3% to 3% | 55 |
| Operating junction temperature range |  | -40 |  | 125 | °C |  | 70 |
| Junction-to-case thermal resistance | θJC |  | 2.897 |  | °C/W |  | 70 |
| Junction-to-ambient thermal resistance | θJA |  | 23.36 |  | °C/W |  | 70 |

## CAD (KiCad official)

- Symbol: `PAC5225QM`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm`
- 3D model: TQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `pac5225qm-etched.step` / `pac5225qm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pac5225qm.step` / `pac5225qm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Qorvo datasheet](docs/pac5225qm-datasheet.pdf) (75 pp, sha256 `ed5b9c4e7a9aa7bf`, retrieved 2026-10-26, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pac5225qm-datasheet.pdf)