PAC1944T-E from Microchip Tech, in a WLCSP-16(2.2x2.2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
C3	SLOW/ALERT1	bidirectional	SLOW input pin: when high, all channels sample at 8 SPS, and the pin may be programmed as the open-drain ALERT1 pin or as a GPIO.
A4	VDD	power_in	Positive power supply input for the device, specified at 2.7V to 5.5V and to be bypassed with a 100 nF ceramic capacitor to ground near the IC.
B4	GND	power_in	System ground for the IC.
C4	SCL	input	SMBus clock input that requires an external pull-up resistor, except in High-Speed mode, which requires a CMOS driver from the host.
D4	SDA	bidirectional	Bidirectional SMBus open-drain data pin that requires a pull-up resistor to VDD.
C2	ADDRSEL	passive	Address selection pin: a resistor connected from this pin to ground selects the SMBus client address.
C1	SENSE3-	passive	Channel 3 differential sense input (0 to FSR), connected to the load side of the sense resistor.
D1	SENSE3+	passive	Channel 3 differential sense input (0 to FSR), connected to the supply side of the sense resistor, which also serves as the bus voltage input.
D2	SENSE4-	passive	Channel 4 differential sense input (0 to FSR), connected to the load side of the sense resistor.
D3	SENSE4+	passive	Channel 4 differential sense input (0 to FSR), connected to the supply side of the sense resistor, which also serves as the bus voltage input.
A3	SENSE1+	passive	Channel 1 differential sense input (0 to FSR), connected to the supply side of the sense resistor, which also serves as the bus voltage input.
A2	SENSE1-	passive	Channel 1 differential sense input (0 to FSR), connected to the load side of the sense resistor.
A1	SENSE2+	passive	Channel 2 differential sense input (0 to FSR), connected to the supply side of the sense resistor, which also serves as the bus voltage input.
B1	SENSE2-	passive	Channel 2 differential sense input (0 to FSR), connected to the load side of the sense resistor.
B2	GPIO/ALERT2	bidirectional	Defaults to a GPIO input and may be programmed as the open-drain ALERT2 pin or as an open-drain GPIO output, requiring a pull-up resistor to VDD.
B3	PWRDN	input	Active-low power-down input that places the device in a Power-Down state in which all circuitry, including SMBus, is powered down.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	WLCSP-16(2.2x2.2)
Category	Power Management (PMIC)
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD Range	VDD	2.7		5.5	V		6
VDD Active Current	IDD		395	495	µA	1024 SPS, 4 channels enabled	6
VDD Active Current	IDD		395	440	µA	1024 SPS, 4 channels enabled, TA = 0°C to +85°C	6
VDD Active Current	IDD		12	25	µA	8 SPS, 4 channels enabled, TA = 0°C to +85°C	6
VDD Power-Down Current	IDD_PWRDN	0		8	µA		6
Bus Voltage Range	VBUS	-0.2		9	V	Common-mode voltage on SENSE pins, referenced to ground	6
VSENSE Differential Input Voltage Range	VSENSE_DIF	-100		100	mV		6
SENSE+, SENSE- Pin Input Current	ISENSE+, ISENSE-	-6	0.6	6	µA	VSENSE+ = VSENSE- = Full scale	6
SENSE+, SENSE- Pin Input Current	ISENSE+, ISENSE-	-1	0.4	1	µA	VSENSE+ = 6V, VSENSE- = 5.9V	6
VSENSE ADC Data Resolution	VSENSE_RES			16	Bits		6
VBUS ADC Data Resolution	VBUS_RES			16	Bits	14 bits are used for power calculations, 16 bits are reported when the VBUS measurement result is read	6
VSENSE Gain Accuracy	VSENSE_GAIN_ERR	-0.5		0.5	%	At +25°C typical, -40°C to +125°C	6
VSENSE Offset Accuracy, Referenced to Input	VSENSE_OFFSET_ERR	-100		100	µV	16-bit resolution	7
VBUS Gain Accuracy	VBUS_GAIN_ERR	-0.25		0.25	%	At +25°C typical, -40°C to +125°C	7
Accumulator Error	ACC_Err		0.1		%	1 Sigma Error Range with >1000 Accumulations, VSENSE = 97 mV	7
Accumulator Error	ACC_Err		1		%	1 Sigma Error Range with >1000 Accumulations, VSENSE = 1 mV	7
Accumulator Error	ACC_Err		2		%	1 Sigma Error Range with >1000 Accumulations, VSENSE = 100 µV	7
Accumulator Error	ACC_Err		4		%	1 Sigma Error Range with >1000 Accumulations, VSENSE = 50 µV	7
Time to First Communications	tINT_T			50	ms	Time after VDD is applied before it is ready to begin communication and measurement.	7
Transition from Sleep State to Start of Conversion Cycle	tSLEEP_TO_ACTIVE			5	ms	Time from Sleep state exit commanded by register write to the beginning of the conversion cycle.	7
Input High Voltage	VIH	1.35			V	Digital I/O Pins (SLOW/ALERT, SM_CLK, SM_DATA Pins)	7
Input Low Voltage	VIL			0.8	V	Digital I/O Pins (SLOW/ALERT, SM_CLK, SM_DATA Pins)	7
Output Low Voltage	VOL			0.4	V	Sinking 8 mA for the ALERT pins and 20 mA for the CLK pin in all modes. 4 mA for the SDA pin in 3.4 MHz mode.	7
Leakage Current	ILEAK	-0.5		0.5	µA	Powered or unpowered	7
Input High Voltage	VIH	1.3			V	Digital I/O Pin (PWRDN)	7
Input Low Voltage	VIL			0.6	V	Digital I/O Pin (PWRDN)	7
VDD Pin	VDD	-0.3		6	V		5
Voltage on SENSE- and SENSE+ Pins		-0.3		40	V		5
Voltage on Any Other Pin to GND		-0.3		6	V		5
Input Current to Any Pin Except VDD		-100		100	mA		5
Operating Ambient Temperature Range	TA	-40		150	°C		5
Storage Temperature Range	TSTG	-55		150	°C		5
Specified Temperature Range	TA	-40		125	°C		9
Operating Temperature Range	TA	-40		125	°C		9
Clock Frequency	fSMB	0.01		1	MHz	Fast Mode Plus. No minimum if Time-out is not enabled.	8
Clock Frequency	fSMB	0.01		3.4	MHz	High-Speed mode. No minimum if Time-out is not enabled.	8
Spike Suppression	tSP	0		50	ns	Fast Mode Plus	8
Spike Suppression	tSP	0		10	ns	High-Speed mode	8
Hold Time after Repeated Start Condition	tHD:STA	0.26			µs	Per SMBus 3.1, Fast Mode Plus	8
Hold Time after Repeated Start Condition	tHD:STA	0.16			µs	Per SMBus 3.1, High-Speed mode	8
Repeated Start Condition Setup Time	tSU:STA	0.26			µs	Per SMBus 3.1, Fast Mode Plus	8
Repeated Start Condition Setup Time	tSU:STA	0.16			µs	Per SMBus 3.1, High-Speed mode	8
Data Hold Time	tHD:DAT	0			ns	Per SMBus 3.1, Fast Mode Plus	8
Data Hold Time	tHD:DAT	0		70	ns	Per SMBus 3.1, High-Speed mode	8
Data Setup Time	tSU:DAT	50			ns	Per SMBus 3.1, Fast Mode Plus	8
Data Setup Time	tSU:DAT	10			ns	Per SMBus 3.1, High-Speed mode	8
Clock Low Period	tLOW	0.5			µs	Per SMBus 3.1, Fast Mode Plus	8
Clock Low Period	tLOW	0.16			µs	Per SMBus 3.1, High-Speed mode	8
Clock High Period	tHIGH	0.26		50	µs	Fast Mode Plus	8
Clock High Period	tHIGH	0.06		50	µs	High-Speed mode	8
Capacitive Load	CLOAD			550	pF	Per bus line, Fast Mode Plus	9
Capacitive Load	CLOAD			100	pF	Per bus line, High-Speed mode	9
SLOW Pin Pulse Width	SLOWpw	150			µs	Pulses narrower than 150 µS may not be detected	9
Thermal Resistance, 16-Ball WLCSP	JA		51.16		°C/W	16-Lead WLCSP	9
Thermal Resistance, 16-Ball WLCSP	JC		4.85		°C/W	16-Lead WLCSP	9

CAD (KiCad official)

Symbol: PAC1944T-E
Footprint: Package_CSP:WLCSP-16_2.225x2.17mm_Layout4x4_P0.5mm
3D model: WLCSP-16(2.2x2.2) (KiCad packages3D, STEP)
3D model files: pac1944t-e-etched.step / pac1944t-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pac1944t-e.step / pac1944t-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (96 pp, sha256 e4f3260d6efac29e, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

PAC1944T-E

Changed since verified PAC1944T-E

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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