component
PAC1720-1-AIA-TR
Public Made by Adomby adom
Microchip Tech Current-Sensing Amplifiers, WDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPAC1720-1-AIA-TR
Microchip Tech · Current-Sensing Amplifiers · WDFN-10-EP(3x3)
PAC1720-1-AIA-TR from Microchip Tech, in a WDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE1+ | input | VBUS1/VSENSE1+ positive sense input for channel 1 and bus voltage input, analog pin with maximum voltage of 40V. |
| 2 | SENSE1- | input | VSENSE1- negative sense input for channel 1, analog pin with maximum voltage of 40V. |
| 3 | SENSE2+ | input | VBUS2/VSENSE2+ positive sense input for channel 2 and bus voltage input (PAC1720 only), analog pin with maximum voltage of 40V. |
| 4 | SENSE2- | input | VSENSE2- negative sense input for channel 2 (PAC1720 only), analog pin with maximum voltage of 40V. |
| 5 | GND | power_in | System ground. |
| 6 | ADDR_SEL | input | Selects the SMBus/I2C slave address based on a pull-down resistor. |
| 7 | ALERT | output | SMBus ALERT digital output asserted under fault conditions. |
| 8 | SMDATA | bidirectional | Bidirectional SMBus data pin, open drain, requires a pull-up resistor. |
| 9 | SMCLK | input | SMBus clock digital input, open drain, requires a pull-up resistor. |
| 10 | VDD | power_in | Positive power supply input, 3.0V to 5.5V. |
| 11 | EP | passive | Exposed thermal pad, not internally connected, recommended to be connected to ground for noise immunity. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | WDFN-10-EP(3x3) |
| Category | Operational Amplifier/Comparator |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Range | VDD | 3 | 5.5 | V | 4 | ||
| Voltage on SENSE+ | VSOURCE | 0 | 40 | V | 4 | ||
| VDD Pin Supply Current (PAC1720), continuous | IDD | 0.525 | 1.3 | mA | Both measurement channels enabled. Continuous conversions | 4 | |
| VDD Pin Supply Current (PAC1720), one conversion per second | IDD | 13 | 50 | µA | Both channels enabled. One conversion per second; VSRC_SAMP_TIME = 2.5 ms; CS_SAMP_TIME = 2.5 ms; No SMBus communications | 4 | |
| VDD Rise Rate | VDD_RISE | 0.03 | V/ms | 0 to 3V in 100 ms | 4 | ||
| VDD Standby Current | IDD_STBY | 5.5 | 15 | µA | Standby state | 4 | |
| SENSE Common-Mode Voltage Range | VCM | 0 | 40 | V | Common-mode voltage on SENSE pins, referenced to ground | 4 | |
| VSENSE Differential Input Voltage Range | VDIFF | -80 | 80 | mV | Voltage between SENSE+ and SENSE- pins | 4 | |
| Common-Mode Rejection | VSENSE_CMRR | 80 | 100 | dB | 0V < VSOURCE < 40V | 4 | |
| VBUS Gain Accuracy | VBUS_GAIN_ERR | 0.4 | % | Measured at ADC output, Gain = 1 (printed ±0.4) | 4 | ||
| SENSE pin leakage, sleep | ISENSE+, ISENSE- | 1 | µA | VBUS = 24V, VSENSE = 0V; Sleep state | 5 | ||
| SENSE pin leakage, VDD=0 | ISENSE+, ISENSE- | 1 | µA | VDD = 0V | 5 | ||
| SENSE+ Pin Bias Current | ISENSE+ | 100 | 150 | µA | -80 mV < VSENSE < 80 mV; Active state | 5 | |
| SENSE- Pin Bias Current | ISENSE- | 0.1 | 1 | µA | -80 mV < VSENSE < 80 mV; Active state | 5 | |
| Total Error positive range | VSENSE_TOT_ERR | 0.5 | 1 | % FSR | FSR = 0 to +10 mV | 5 | |
| Total Error positive range | VSENSE_TOT_ERR | 0.3 | 0.6 | % FSR | FSR = 0 to +20 mV | 5 | |
| Total Error positive range | VSENSE_TOT_ERR | 0.2 | 0.4 | % FSR | FSR = 0 to +40 mV | 5 | |
| Total Error negative range | VSENSE_TOT_ERR | -1 | -1.3 | -1.6 | % FSR | FSR = -10 mV to 0 | 5 |
| Total Error negative range | VSENSE_TOT_ERR | -1.6 | -2 | -2.4 | % FSR | FSR = -80 mV to 0 | 5 |
| VSOURCE Error | VSOURCE_ERR | 0.15 | 0.3 | % FSV | (±) | 5 | |
| Total Power Ratio Error positive range | PRATIO_ERR | 1 | % FSR | FSR = 0 to +10 mV, 0 to +20 mV, 0 to +40 mV, or 0 to +80 mV | 6 | ||
| Total Power Ratio Error negative range | PRATIO_ERR | 2 | % FSR | FSR = -10 mV to 0, -20 mV to 0, -40 mV to 0, or -80 mV to 0 | 6 | ||
| First Power Ratio Ready | tCONV_P | 220 | ms | Time after power-up before PRATIO updated | 6 | ||
| Pull-up Voltage Range | VPULLUP | 3 | 5.5 | V | Pull-up voltage for SMBus and ALERT pins | 6 | |
| Time to First Communications | tCOMM | 25 | ms | 6 | |||
| Input High Voltage | VIH | 2 | V | SMCLK, SMDATA | 6 | ||
| Input Low Voltage | VIL | 0.8 | V | 6 | |||
| Output Low Voltage | VOL | 0.4 | V | OD pin pulled to VPULLUP; 3 mA current sink | 6 | ||
| Leakage Current | ILEAK | 5 | µA | Powered or unpowered; TA < +85°C | 6 | ||
| SMBus Input Capacitance | CIN | 4 | 10 | pF | 7 | ||
| SMBus Clock Frequency | fSMB | 10 | 400 | kHz | 7 | ||
| Spike Suppression | tSP | 100 | ns | 7 | |||
| Bus Free Time Stop to Start | tBUF | 1.3 | µs | 7 | |||
| Start Setup Time | tSU:STA | 0.6 | µs | 7 | |||
| Start Hold Time | tHD:STA | 0.6 | µs | 7 | |||
| Stop Setup Time | tSU:STO | 0.6 | µs | 7 | |||
| Data Hold Time | tHD:DAT | 0 | µs | When transmitting to the master | 7 | ||
| Data Hold Time | tHD:DAT | 0.3 | µs | When receiving from the master | 7 | ||
| Data Setup Time | tSU:DAT | 0.6 | µs | 7 | |||
| Clock Low Period | tLOW | 1.3 | µs | 7 | |||
| Clock High Period | tHIGH | 0.6 | µs | 7 | |||
| Clock/Data Fall Time | tFALL | 300 | ns | Min = 20 + 0.1 CLOAD ns | 7 | ||
| Clock/Data Rise Time | tRISE | 300 | ns | Min = 20 + 0.1 CLOAD ns | 7 | ||
| Capacitive Load | CLOAD | 400 | pF | Total per bus line | 7 | ||
| VDD pin | VDD | -0.3 | 6 | V | 3 | ||
| Voltage on SENSE- and SENSE+ pins | -0.3 | 42 | V | 3 | |||
| Voltage on any other pin to GND | -0.3 | V | -GND-0.3 to VDD+0.3V (max VDD+0.3) | 3 | |||
| Voltage between Sense pins | 40 | V | /(SENSE+, SENSE-)/ | 3 | |||
| Input current to any pin except VDD | 10 | mA | 3 | ||||
| Package Power Dissipation | 0.5 | W | up to TA = +85°C | 3 | |||
| Operating Ambient Temperature Range | TA | 0 | 85 | °C | 3 | ||
| Storage Temperature Range | -55 | 150 | °C | 3 | |||
| ESD HBM SMCLK, SMDATA, ALERT | 8000 | V | HBM | 3 | |||
| ESD HBM all other pins | 2000 | V | HBM | 3 | |||
| Junction to Ambient | θJ-A | 78 | °C/W | 3 | |||
| Offset Error Voltage FSR ±80 mV | VOS | 40 | µV | FSR = ±80 mV (printed ±40) | 5 |
CAD (KiCad official)
- Symbol:
PAC1720-1-AIA-TR - Footprint:
Package_DFN_QFN:WDFN-10-1EP_3x3mm_P0.5mm_EP1.8x2.5mm - 3D model: WDFN-10-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
pac1720-1-aia-tr-etched.step/pac1720-1-aia-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pac1720-1-aia-tr.step/pac1720-1-aia-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (48 pp, sha256
d4936cbfd55b88c2, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).