P9148NRGI8 from RENESAS, in a DFN-12(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DIF	input	Digital interface to the host PMIC: 1.8V logic input.
2	SGND	power_in	DIF/DIO signal ground reference: connect directly to the ground plane.
3	RSET	passive	Connect to the device identification/configuration resistor (RSET pin rated -0.3V to 6.0V).
4	LX	passive	Switching node inductor connection: connect to either a 0.47µH or 1µH inductor depending on the application.
5	LX	passive	Switching node inductor connection: connect to either a 0.47µH or 1µH inductor depending on the application.
6	LX	passive	Switching node inductor connection: connect to either a 0.47µH or 1µH inductor depending on the application.
7	PVIN	power_in	Power supply input (4.5V to 8.4V operating, 9.6V abs max): connect 2x10µF capacitors directly between the PVIN pins and PGND EPAD (no via).
8	PVIN	power_in	Power supply input (4.5V to 8.4V operating, 9.6V abs max): connect 2x10µF capacitors directly between the PVIN pins and PGND EPAD (no via).
9	PVIN	power_in	Power supply input (4.5V to 8.4V operating, 9.6V abs max): connect 2x10µF capacitors directly between the PVIN pins and PGND EPAD (no via).
10	VPG	passive	High-side regulator output capacitor connection: connect a 2.2µF capacitor directly between VPG and PVIN pin (no vias).
11	VSYS	passive	Low-side regulator output capacitor connection: connect a 2.2µF capacitor directly between VSYS and the PGND EPAD (no vias).
12	DIO	bidirectional	Digital interface to the host PMIC: bi-directional 1.8V logic input and open-drain output.
13	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	DFN-12(3x4)
Category	Power Management (PMIC)
Pins	13

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Voltage Range	VPVIN	4.5		8.4	V		6
PVIN Under-Voltage Lock-Out rising threshold	VUV	4.35	4.4	4.45	V	PVIN rising threshold	6
PVIN Under-Voltage Lock-Out falling threshold	VUV	3.95	4	4.05	V	PVIN falling threshold	6
Shutdown Current	ISHDN		1	10	μA	DIO = 0V	6
Quiescent Current Standby	IQ		180	210	μA	Standby Mode: DIO = HIGH, DIF = LOW	6
Quiescent Current Idle	IQ		520	600	μA	Idle Mode: DIO = HIGH, DIF = active, LX not switching	6
Operating Supply Current	IOP		18	30	mA	Active Mode, switching, no load	6
LX Peak Current Limit	ILIM	6		6.5	A	Occurs at maximum DIF duty-cycle of 83%	6
Thermal Shutdown Temperature	TSD		127	135	°C	Guaranteed by design	6
DIO Output LOW Voltage	VOL			0.4	V	At IOL = 12mA (open-drain output)	6
LOW Level Input Voltage	VIL			0.65	V		6
HIGH Level Input Voltage	VIH	1.15			V		6
Continuous Output Current	IOUT		4.5		A	TJ < 115°C, Guaranteed by design	6
Maximum Pulse Load Current	IPULSE		6		A	Pulse duration < 1ms, Pulse duty-cycle < 0.1%	6
High-Side Switch On-Resistance	R(on)		55		mΩ	High-Side Switch	6
Low-Side Switch On-Resistance	R(on)		30		mΩ	Low-Side Switch	6
Low-Side LDO Output Voltage	VSYS		4.8		V		6
Thermal Shutdown Delay	tSDDLY		4		ms		6
Input De-glitch Time	tDG		4		ns		7
DIF Input Frequency	fDIF		4		MHz	Informative only	7
Device Start-up Time	tST		300		µs	From DIO assertion	7
PVIN Pin		-0.3		9.6	V		5
VSYS, RSET Pins		-0.3		6	V		5
DIF, DIO Pins		-0.3		2.2	V		5
LX Pin DC Voltage		-0.3		9.6	V	Time > 500ns	5
LX Pin AC Voltage		-1.2		16	V	Time < 500ns	5
PVIN Pin to VPG Pin		-0.3		6	V	printed as < 6.0	5
ESD Human Body Model		-1000		1000	V	All Pins	5
ESD Charge Device Model		-500		500	V	All Pins	5
Junction Temperature	TJ	-40		125	C		5
Storage Temperature	TSTG	-55		150	C		5
Lead Temperature	TLEAD			300	C	soldering, 10s	5
Ambient Operating Temperature	TA	-40		85	C		5
Thermal Resistance Junction to Ambient	θJA		36		C/W	JEDEC 4-layer PCB, still air	5
Thermal Resistance Junction to Top of Case	θJC(T)		66		C/W	JEDEC 4-layer PCB, still air	5
Thermal Resistance Junction to Bottom of Case	θJC(B)		0.8		C/W	JEDEC 4-layer PCB, still air	5

CAD (KiCad official)

Symbol: P9148NRGI8
Footprint: Package_DFN_QFN:DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm
3D model: DFN-12(3x4) (KiCad packages3D, STEP)
3D model files: p9148nrgi8-etched.step / p9148nrgi8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p9148nrgi8.step / p9148nrgi8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (20 pp, sha256 e351aa3cc0c0e5d2, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

P9148NRGI8

Verified P9148NRGI8

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README