component
P25Q64SH-SSH-IT
Public Made by Adomby adom
PUYA) NOR FLASH, SOP-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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P25Q64SH-SSH-IT
PUYA) · NOR FLASH · SOP-8-150mil
P25Q64SH-SSH-IT from PUYA), in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select input; the device is selected when this active-low pin is driven low. |
| 2 | SO | bidirectional | Serial data output for 1x I/O, and serial data input and output (SIO1) for 2x and 4x I/O read modes. |
| 3 | WP# | bidirectional | Write protection input, active low, with weak internal pull-up; also serves as SIO2 for 4x I/O read mode. WP# function is only available for Standard/Dual SPI with QE=0. |
| 4 | GND | power_in | Ground of the device. |
| 5 | SI | bidirectional | Serial data input for 1x I/O, and serial data input and output (SIO0) for 2x and 4x I/O read modes. |
| 6 | SCLK | input | Serial interface clock input. |
| 7 | HOLD#/RESET# | bidirectional | Active-low hardware reset, or pauses the device without deselecting it; weak internal pull-up, also serves as SIO3 for 4x I/O read mode. HOLD#/RESET# function is only available for Standard/Dual SPI with QE=0. |
| 8 | VCC | power_in | Power supply of the device, 2.3V to 3.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PUYA) |
| Package | SOP-8-150mil |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Deep power down current | IDPD | 0.3 | 5 | uA | CS#=VCC, all other inputs at 0V or VCC | 9 | |
| Standby current | ISB | 10 | 18 | uA | CS#, HOLD#, WP#=VIH all inputs at CMOS levels | 9 | |
| Low power read current (03h), f=1MHz | ICC1 | 0.3 | 0.5 | mA | f=1MHz; IOUT=0mA | 9 | |
| Low power read current (03h), f=33MHz | ICC1 | 1.5 | 3 | mA | f=33MHz; IOUT=0mA | 9 | |
| All Read current | ICC2_DC | 0.3 | 0.5 | mA | IOUT=0mA | 9 | |
| Read current, SPI(STR,x1) | ICC2_AC | 0.04 | 0.06 | mA/MHz | IOUT=0mA | 9 | |
| Read current, DSPI(STR,x2) | ICC2_AC | 0.052 | 0.08 | mA/MHz | IOUT=0mA | 9 | |
| Read current, QSPI/QPI(STR) | ICC2_AC | 0.08 | 0.12 | mA/MHz | IOUT=0mA | 9 | |
| Read current, SPI(DTR,x1) | ICC2_AC | 0.06 | 0.09 | mA/MHz | IOUT=0mA | 9 | |
| Read current, DSPI(DTR,x2) | ICC2_AC | 0.09 | 0.13 | mA/MHz | IOUT=0mA | 9 | |
| Read current, QSPI/QPI(DTR) | ICC2_AC | 0.135 | 0.19 | mA/MHz | IOUT=0mA | 9 | |
| Program current | ICC3 | 3 | 5 | mA | CS#=VCC | 9 | |
| Erase current | ICC4 | 3 | 5 | mA | CS#=VCC | 9 | |
| Input load current | ILI | 2 | uA | All inputs at CMOS level | 9 | ||
| Output leakage | ILO | 2 | uA | All inputs at CMOS level | 9 | ||
| Input low voltage | VIL | 0.3 | Vcc | 9 | |||
| Input high voltage | VIH | 0.7 | Vcc | 9 | |||
| Output low voltage | VOL | 0.2 | V | IOL=100uA | 9 | ||
| Clock Frequency for all instructions except special marking | fSCLK | 120 | MHz | 10 | |||
| Clock Frequency for READ instructions | fRSCLK | 55 | MHz | READ instructions | 10 | ||
| Clock Frequency for 2READ, DREAD instructions | fTSCLK | 120 | MHz | 2READ, DREAD instructions | 10 | ||
| Clock Frequency for 4READ, QREAD, QPI instructions | fQ | 120 | MHz | 4READ, QREAD, QPI 0Bh, QPI EBh, QPI 0Ch instructions | 10 | ||
| Clock Frequency for DTR 1IO/2IO instructions | fD | 85 | MHz | DTR 1IO/2IO instructions | 10 | ||
| Clock Frequency for DTR 4IO instructions | fQD | 70 | MHz | DTR 4IO instructions | 10 | ||
| Clock Frequency for QPP (Quad page program) | fQPP | 120 | MHz | Quad page program | 10 | ||
| Program Suspend Latency | tPSL | 20 | us | 11 | |||
| Erase Suspend Latency | tESL | 20 | us | 11 | |||
| Latency between Program Resume and next Suspend | tPRS | 20 | us | 11 | |||
| Latency between Erase Resume and next Suspend | tERS | 20 | us | 11 | |||
| Page program time (up to 256/512/1024 bytes) | tPP | 1.6 | 2.5 | ms | up to 256/512/1024 bytes | 11 | |
| Page erase time | tPE | 16 | 25 | ms | 11 | ||
| Sector erase time | tSE | 16 | 25 | ms | 11 | ||
| Block erase time for 32K bytes | tBE1 | 16 | 25 | ms | 11 | ||
| Block erase time for 64K bytes | tBE2 | 16 | 25 | ms | 11 | ||
| Chip erase time | tCE | 256 | 400 | ms | 11 | ||
| Output Capacitance | COUT | 8 | pF | VOUT=GND | 8 | ||
| Input Capacitance | CIN | 6 | pF | VIN=GND | 8 | ||
| Storage Temperature | -65 | 150 | °C | 8 | |||
| Operation Temperature | -40 | 85 | °C | 8 | |||
| Maximum Operation Voltage | 4 | V | 8 | ||||
| Voltage on Any Pin with respect to Ground | -0.6 | V | Printed maximum is VCC+0.5V (not a number); max left null | 8 | |||
| DC Output Current | 5 | mA | 8 | ||||
| Supply voltage (Single supply) | Vcc | 2.3 | 3.6 | V | Single supply for Read, Erase and Program (Overview, datasheet states 2.3V to 3.60V) | 4 | |
| Clock High Time | tCH | 3.7 | ns | 10 | |||
| Clock Low Time | tCL | 3.7 | ns | 45% x (1/fSCLK) | 10 | ||
| CS# Deselect Time from Read to next Read | tSHSL | 20 | ns | 10 | |||
| CS# Deselect Time from Write, Erase, Program to Read Status Register | tSHSL | 30 | ns | 10 | |||
| Data in Setup Time | tDVCH | 2 | ns | 10 | |||
| Data in Hold Time | tCHDX | 3 | ns | 10 | |||
| Output Disable Time | tSHQZ | 6 | ns | 10 | |||
| Clock Low to Output Valid | tCLQV | 1.5 | 6 | ns | Loading 30pF | 10 | |
| Clock Low to Output Valid | tCLQV | 1.5 | 5 | ns | Loading 15pF | 10 | |
| Output Hold Time | tCLQX | 0.8 | ns | 10 | |||
| CS# High to Deep Power-down Mode | tDP | 3 | us | 10 | |||
| CS# High to Standby Mode Without Electronic Signature Read | tRES1 | 8 | us | 10 | |||
| Write Status Register Cycle Time | tW | 8 | 12 | ms | 10 | ||
| Reset recovery time (for erase/program operation except WRSR) | tReady | 30 | us | erase/program operation except WRSR | 10 | ||
| Clear Page Buffer time | tBC | 0.3 | us | 10 | |||
| Clock Low Time for READ instructions setup-sequence: CS# Active Setup Time (relative to SCLK) | tSLCH | 5 | ns | 10 | |||
| CS# Not Active Hold Time (relative to SCLK) | tCHSL | 5 | ns | 10 |
CAD (KiCad official)
- Symbol:
P25Q64SH-SSH-IT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-150mil (KiCad packages3D, STEP)
- 3D model files:
p25q64sh-ssh-it-etched.step/p25q64sh-ssh-it-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);p25q64sh-ssh-it.step/p25q64sh-ssh-it.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PUYA) datasheet (104 pp, sha256
13fbd52e680d2010, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# P25Q64SH-SSH-IT
**PUYA)** · NOR FLASH · SOP-8-150mil
P25Q64SH-SSH-IT from PUYA), in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select input; the device is selected when this active-low pin is driven low. |
| 2 | SO | bidirectional | Serial data output for 1x I/O, and serial data input and output (SIO1) for 2x and 4x I/O read modes. |
| 3 | WP# | bidirectional | Write protection input, active low, with weak internal pull-up; also serves as SIO2 for 4x I/O read mode. WP# function is only available for Standard/Dual SPI with QE=0. |
| 4 | GND | power_in | Ground of the device. |
| 5 | SI | bidirectional | Serial data input for 1x I/O, and serial data input and output (SIO0) for 2x and 4x I/O read modes. |
| 6 | SCLK | input | Serial interface clock input. |
| 7 | HOLD#/RESET# | bidirectional | Active-low hardware reset, or pauses the device without deselecting it; weak internal pull-up, also serves as SIO3 for 4x I/O read mode. HOLD#/RESET# function is only available for Standard/Dual SPI with QE=0. |
| 8 | VCC | power_in | Power supply of the device, 2.3V to 3.6V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PUYA) |
| Package | SOP-8-150mil |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Deep power down current | IDPD | | 0.3 | 5 | uA | CS#=VCC, all other inputs at 0V or VCC | 9 |
| Standby current | ISB | | 10 | 18 | uA | CS#, HOLD#, WP#=VIH all inputs at CMOS levels | 9 |
| Low power read current (03h), f=1MHz | ICC1 | | 0.3 | 0.5 | mA | f=1MHz; IOUT=0mA | 9 |
| Low power read current (03h), f=33MHz | ICC1 | | 1.5 | 3 | mA | f=33MHz; IOUT=0mA | 9 |
| All Read current | ICC2_DC | | 0.3 | 0.5 | mA | IOUT=0mA | 9 |
| Read current, SPI(STR,x1) | ICC2_AC | | 0.04 | 0.06 | mA/MHz | IOUT=0mA | 9 |
| Read current, DSPI(STR,x2) | ICC2_AC | | 0.052 | 0.08 | mA/MHz | IOUT=0mA | 9 |
| Read current, QSPI/QPI(STR) | ICC2_AC | | 0.08 | 0.12 | mA/MHz | IOUT=0mA | 9 |
| Read current, SPI(DTR,x1) | ICC2_AC | | 0.06 | 0.09 | mA/MHz | IOUT=0mA | 9 |
| Read current, DSPI(DTR,x2) | ICC2_AC | | 0.09 | 0.13 | mA/MHz | IOUT=0mA | 9 |
| Read current, QSPI/QPI(DTR) | ICC2_AC | | 0.135 | 0.19 | mA/MHz | IOUT=0mA | 9 |
| Program current | ICC3 | | 3 | 5 | mA | CS#=VCC | 9 |
| Erase current | ICC4 | | 3 | 5 | mA | CS#=VCC | 9 |
| Input load current | ILI | | | 2 | uA | All inputs at CMOS level | 9 |
| Output leakage | ILO | | | 2 | uA | All inputs at CMOS level | 9 |
| Input low voltage | VIL | | | 0.3 | Vcc | | 9 |
| Input high voltage | VIH | 0.7 | | | Vcc | | 9 |
| Output low voltage | VOL | | | 0.2 | V | IOL=100uA | 9 |
| Clock Frequency for all instructions except special marking | fSCLK | | | 120 | MHz | | 10 |
| Clock Frequency for READ instructions | fRSCLK | | | 55 | MHz | READ instructions | 10 |
| Clock Frequency for 2READ, DREAD instructions | fTSCLK | | | 120 | MHz | 2READ, DREAD instructions | 10 |
| Clock Frequency for 4READ, QREAD, QPI instructions | fQ | | | 120 | MHz | 4READ, QREAD, QPI 0Bh, QPI EBh, QPI 0Ch instructions | 10 |
| Clock Frequency for DTR 1IO/2IO instructions | fD | | | 85 | MHz | DTR 1IO/2IO instructions | 10 |
| Clock Frequency for DTR 4IO instructions | fQD | | | 70 | MHz | DTR 4IO instructions | 10 |
| Clock Frequency for QPP (Quad page program) | fQPP | | | 120 | MHz | Quad page program | 10 |
| Program Suspend Latency | tPSL | | | 20 | us | | 11 |
| Erase Suspend Latency | tESL | | | 20 | us | | 11 |
| Latency between Program Resume and next Suspend | tPRS | | | 20 | us | | 11 |
| Latency between Erase Resume and next Suspend | tERS | | | 20 | us | | 11 |
| Page program time (up to 256/512/1024 bytes) | tPP | | 1.6 | 2.5 | ms | up to 256/512/1024 bytes | 11 |
| Page erase time | tPE | | 16 | 25 | ms | | 11 |
| Sector erase time | tSE | | 16 | 25 | ms | | 11 |
| Block erase time for 32K bytes | tBE1 | | 16 | 25 | ms | | 11 |
| Block erase time for 64K bytes | tBE2 | | 16 | 25 | ms | | 11 |
| Chip erase time | tCE | | 256 | 400 | ms | | 11 |
| Output Capacitance | COUT | | | 8 | pF | VOUT=GND | 8 |
| Input Capacitance | CIN | | | 6 | pF | VIN=GND | 8 |
| Storage Temperature | | -65 | | 150 | °C | | 8 |
| Operation Temperature | | -40 | | 85 | °C | | 8 |
| Maximum Operation Voltage | | | | 4 | V | | 8 |
| Voltage on Any Pin with respect to Ground | | -0.6 | | | V | Printed maximum is VCC+0.5V (not a number); max left null | 8 |
| DC Output Current | | | | 5 | mA | | 8 |
| Supply voltage (Single supply) | Vcc | 2.3 | | 3.6 | V | Single supply for Read, Erase and Program (Overview, datasheet states 2.3V to 3.60V) | 4 |
| Clock High Time | tCH | 3.7 | | | ns | | 10 |
| Clock Low Time | tCL | 3.7 | | | ns | 45% x (1/fSCLK) | 10 |
| CS# Deselect Time from Read to next Read | tSHSL | 20 | | | ns | | 10 |
| CS# Deselect Time from Write, Erase, Program to Read Status Register | tSHSL | 30 | | | ns | | 10 |
| Data in Setup Time | tDVCH | 2 | | | ns | | 10 |
| Data in Hold Time | tCHDX | 3 | | | ns | | 10 |
| Output Disable Time | tSHQZ | | | 6 | ns | | 10 |
| Clock Low to Output Valid | tCLQV | 1.5 | | 6 | ns | Loading 30pF | 10 |
| Clock Low to Output Valid | tCLQV | 1.5 | | 5 | ns | Loading 15pF | 10 |
| Output Hold Time | tCLQX | 0.8 | | | ns | | 10 |
| CS# High to Deep Power-down Mode | tDP | | | 3 | us | | 10 |
| CS# High to Standby Mode Without Electronic Signature Read | tRES1 | | | 8 | us | | 10 |
| Write Status Register Cycle Time | tW | | 8 | 12 | ms | | 10 |
| Reset recovery time (for erase/program operation except WRSR) | tReady | | | 30 | us | erase/program operation except WRSR | 10 |
| Clear Page Buffer time | tBC | | | 0.3 | us | | 10 |
| Clock Low Time for READ instructions setup-sequence: CS# Active Setup Time (relative to SCLK) | tSLCH | 5 | | | ns | | 10 |
| CS# Not Active Hold Time (relative to SCLK) | tCHSL | 5 | | | ns | | 10 |
## CAD (KiCad official)
- Symbol: `P25Q64SH-SSH-IT`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8-150mil (KiCad packages3D, STEP)
- 3D model files: `p25q64sh-ssh-it-etched.step` / `p25q64sh-ssh-it-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `p25q64sh-ssh-it.step` / `p25q64sh-ssh-it.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [PUYA) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757136977857142784) (104 pp, sha256 `13fbd52e680d2010`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/p25q64sh-ssh-it-datasheet.pdf)