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P25Q40SH-TSH-IR

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PUYA） NOR FLASH, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P25Q40SH-TSH-IR

PUYA） · NOR FLASH · TSSOP-8

P25Q40SH-TSH-IR from PUYA）, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip select input, active low, used to select the device for serial operations.
2 SO bidirectional Serial data output for 1 x I/O (SIO1), and serial data input and output for 4 x I/O read mode.
3 WP# bidirectional Write protection input, active low, for hardware protection of protected sectors; also SIO2 for 4 x I/O read mode, and the WP# function is only available for Standard/Dual SPI.
4 GND power_in Ground of the device.
5 SI bidirectional Serial data input for 1 x I/O (SIO0), and serial data input and output for 4 x I/O read mode.
6 SCLK input Serial interface clock input.
7 HOLD#/RESET# bidirectional Active-low hardware reset or hold pin that pauses the device without deselecting it; also SIO3 for 4 x I/O read mode, and the HOLD#/RESET# function is only available for Standard/Dual SPI.
8 VCC power_in Power supply of the device, specified for 2.3V to 3.6V operation.

Key specifications

Parameter Value
Manufacturer PUYA）
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature -65 150 °C 8
Operation Temperature -40 85 °C 8
Maximum Operation Voltage 4 V 8
Voltage on Any Pin with respect to Ground -0.6 4.1 V 8
DC Output Current 5 mA 8
Output Capacitance COUT 8 pF VOUT=GND 8
Input Capacitance CIN 6 pF VIN=GND 8
Single Supply Voltage 2.3 3.6 V 4
Deep power down current IDPD 0.2 2.5 uA CS#=Vcc, all other inputs at 0V or Vcc 9
Standby current ISB 10 uA CS#, HOLD#, WP#=VIH all inputs at CMOS levels 9
Read current (STR) at 33MHz ICC1 2 2.5 mA f=33MHz(03h); IOUT=0mA 9
Read current (STR) at 85MHz ICC1 8 14 mA f=85MHz; IOUT=0mA 9
Read current (STR) at 104MHz ICC1 10 18 mA f=104MHz; IOUT=0mA 9
Program current ICC2 2.5 4 mA CS#=Vcc 9
Erase current ICC3 2.5 4 mA CS#=Vcc 9
Input load current ILI 2 uA All inputs at CMOS level 9
Output leakage ILO 2 uA All inputs at CMOS level 9
Input low voltage VIL 0.3 Vcc 9
Input high voltage VIH 0.7 Vcc 9
Output low voltage VOL 0.2 V IOL=100uA 9
Output high voltage VOH -0.2 V IOH=-100uA 9
Clock Frequency for FREAD, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR fSCLK 104 MHz 10
Clock Frequency for READ instructions fRSCLK 55 MHz 10
Clock Frequency for 2READ, DREAD instructions fTSCLK 104 MHz 10
Clock Frequency for 4READ, QREAD, QPI instructions fQ 104 MHz 4READ, QREAD, QPI 0Bh, QPI EBh, QPI 0Ch instructions 10
Clock High Time tCH 4.5 ns 10
Clock Low Time (fSCLK) tCL 4.5 ns 10
CS# Active Setup Time (relative to SCLK) tSLCH 5 ns 10
CS# Not Active Hold Time (relative to SCLK) tCHSL 5 ns 10
Data In Setup Time tDVCH 2 ns 10
Data In Hold Time tCHDX 3 ns 10
CS# Active Hold Time (relative to SCLK) tCHSH 5 ns 10
CS# Not Active Setup Time (relative to SCLK) tSHCH 5 ns 10
CS# Deselect Time From Read to next Read tSHSL 20 ns From Read to next Read 10
CS# Deselect Time From Write, Erase, Program to Read Status Register tSHSL 30 ns From Write, Erase, Program to Read Status Register 10
Output Disable Time tSHQZ 6 ns 10
Clock Low to Output Valid tCLQV 7 ns Loading 30pF 10
Clock Low to Output Valid tCLQV 6 ns Loading 15pF 10
Output Hold Time tCLQX 0 ns 10
HOLD# to Output Low-Z tHHQX 6 ns 10
HOLD# to Output High-Z tHLQZ 6 ns 10
Write Protect Setup Time tWHSL 20 ns 10
Write Protect Hold Time tSHWL 100 ns 10
CS# High to Deep Power-down Mode tDP 3 us 10
CS# High To Standby Mode Without Electronic Signature Read tRES1 8 us 10
Write Status Register Cycle Time tW 8 12 ms 10
Reset recovery time (for erase/program operation except WRSR) tReady 30 us 10
Reset recovery time (for WRSR operation) tReady 8 12 ms 10
Load memory page data to buffer time (256Byte) tBL 60 100 us 10
Erase Suspend Latency TESL 30 us 12
Program Suspend Latency TPSL 30 us 12
Latency between Program Resume and next Suspend TPRS 20 us 12
Latency between Erase Resume and next Suspend TERS 20 us 12
Page program time (up to 256 bytes) tPP 2 3 ms 12
Page erase time tPE 16 30 ms 12
Sector erase time tSE 16 30 ms 12
Block erase time for 32K bytes tBE1 16 30 ms 12
Block erase time for 64K bytes tBE2 16 30 ms 12
Chip erase time tCE 16 30 ms 12

CAD (KiCad official)

  • Symbol: P25Q40SH-TSH-IR
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: p25q40sh-tsh-ir-etched.step / p25q40sh-tsh-ir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p25q40sh-tsh-ir.step / p25q40sh-tsh-ir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA） datasheet (98 pp, sha256 420957b2119afe9f, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF