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P25Q40L-UXH-IR
Public Made by Adomby adom
PUYA NOR FLASH, USON-8-EP(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownP25Q40L-UXH-IR
PUYA · NOR FLASH · USON-8-EP(2x3)
P25Q40L-UXH-IR from PUYA, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select input for the serial interface. |
| 2 | SO | bidirectional | Serial data output for 1 x I/O; serial data input and output (SIO1) in 4 x I/O read mode. |
| 3 | WP# | bidirectional | Write protection, active low; serial data input and output (SIO2) in 4 x I/O read mode. |
| 4 | GND | power_in | Ground of the device. |
| 5 | SI | bidirectional | Serial data input for 1 x I/O; serial data input and output (SIO0) in 4 x I/O read mode. |
| 6 | SCLK | input | Serial interface clock input. |
| 7 | HOLD# | bidirectional | Pauses the device without deselecting it; serial data input and output (SIO3) in 4 x I/O read mode. |
| 8 | VCC | power_in | Power supply of the device, specified at 1.65V to 2.0V in the Overview. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PUYA |
| Package | USON-8-EP(2x3) |
| Category | Memory |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | -65 | 150 | °C | 8 | |||
| Operation temperature | -40 | 85 | °C | 8 | |||
| Maximum operation voltage | 2.5 | V | 8 | ||||
| Voltage on any pin with respect to ground | -0.6 | 2.5 | V | 8 | |||
| DC output current | 5 | mA | 8 | ||||
| Supply voltage (single supply, read, erase and program) | 1.65 | 2 | V | 4 | |||
| Output capacitance | COUT | 8 | pF | VOUT=GND | 8 | ||
| Input capacitance | CIN | 6 | pF | VIN=GND | 8 | ||
| Deep power down current | IDPD | 0.1 | 0.6 | uA | CS#=Vcc, all other inputs at 0V or Vcc | 9 | |
| Standby current | ISB | 9 | uA | CS#, HOLD#, WP#=VIH all inputs at CMOS levels | 9 | ||
| Low power read current (03h) | ICC1 | 0.5 | 1 | mA | f=1MHz; SO=Open | 9 | |
| Low power read current (03h) | ICC1 | 1 | 2 | mA | f=33MHz; SO=Open | 9 | |
| Read current (0Bh) | ICC2 | 1 | 2 | mA | f=50MHz; SO=Open | 9 | |
| Program current | ICC3 | 1.5 | 3 | mA | CS#=Vcc | 9 | |
| Erase current | ICC4 | 1.5 | 3 | mA | CS#=Vcc | 9 | |
| Input load current | ILI | 1 | uA | All inputs at CMOS level | 9 | ||
| Output leakage | ILO | 1 | uA | All inputs at CMOS level | 9 | ||
| Output low voltage | VOL | 0.2 | V | IOL=100uA | 9 | ||
| Clock frequency for FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR | fSCLK | 85 | MHz | FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR | 10 | ||
| Clock frequency for READ instructions | fRSCLK | 33 | MHz | READ instructions | 10 | ||
| Clock frequency for 2READ, DREAD instructions | fTSCLK | 70 | MHz | 2READ, DREAD instructions | 10 | ||
| Clock frequency for 4READ, QREAD instructions | fQ | 70 | MHz | 4READ, QREAD instructions | 10 | ||
| Clock frequency for QPP (quad page program) | fQPP | 85 | MHz | QPP (Quad page program) | 10 | ||
| Clock high time | tCH | 5.5 | ns | 10 | |||
| Clock low time (fSCLK) | tCL | 5.5 | ns | 10 | |||
| CS# active setup time (relative to SCLK) | tSLCH | 5 | ns | 10 | |||
| CS# not active hold time (relative to SCLK) | tCHSL | 5 | ns | 10 | |||
| Data in setup time | tDVCH | 2 | ns | 10 | |||
| Data in hold time | tCHDX | 3 | ns | 10 | |||
| CS# active hold time (relative to SCLK) | tCHSH | 5 | ns | 10 | |||
| CS# not active setup time (relative to SCLK) | tSHCH | 5 | ns | 10 | |||
| CS# deselect time from read to next read | tSHSL | 15 | ns | From Read to next Read | 10 | ||
| CS# deselect time from write, erase, program to read status register | tSHSL | 30 | ns | From Write, Erase, Program to Read Status Register | 10 | ||
| Output disable time | tSHQZ | 6 | ns | 10 | |||
| Clock low to output valid | tCLQV | 7 | ns | Loading 30pF | 10 | ||
| Clock low to output valid | tCLQV | 6 | ns | Loading 15pF | 10 | ||
| Output hold time | tCLQX | 0 | ns | 10 | |||
| HOLD# active setup time (relative to SCLK) | tHLCH | 5 | ns | 10 | |||
| HOLD# active hold time (relative to SCLK) | tCHHH | 5 | ns | 10 | |||
| HOLD# not active setup time (relative to SCLK) | tHHCH | 5 | ns | 10 | |||
| HOLD# not active hold time (relative to SCLK) | tCHHL | 5 | ns | 10 | |||
| HOLD# to output low-Z | tHHQX | 6 | ns | 10 | |||
| HOLD# to output high-Z | tHLQZ | 6 | ns | 10 | |||
| Write protect setup time | tWHSL | 20 | ns | 10 | |||
| Write protect hold time | tSHWL | 100 | ns | 10 | |||
| CS# high to deep power-down mode | tDP | 3 | us | 10 | |||
| Write status register cycle time | tW | 8 | 12 | ms | 10 | ||
| Erase suspend latency | TESL | 30 | us | 11 | |||
| Program suspend latency | TPSL | 30 | us | 11 | |||
| Page program time (up to 256 bytes) | tPP | 2 | 3 | ms | up to 256 bytes | 11 | |
| Page erase time | tPE | 8 | 12 | ms | 11 | ||
| Sector erase time | tSE | 8 | 12 | ms | 11 | ||
| Block erase time for 32K bytes | tBE1 | 8 | 12 | ms | for 32K bytes | 11 | |
| Block erase time for 64K bytes | tBE2 | 8 | 12 | ms | for 64K bytes | 11 | |
| Chip erase time | tCE | 8 | 12 | ms | 11 |
CAD (KiCad official)
- Symbol:
P25Q40L-UXH-IR - Footprint:
Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm - 3D model: USON-8-EP(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
p25q40l-uxh-ir-etched.step/p25q40l-uxh-ir-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);p25q40l-uxh-ir.step/p25q40l-uxh-ir.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PUYA datasheet (73 pp, sha256
ec3e40aaaa00c98a, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).