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P25D80SH-SSH-IT

Public Made by Adom

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PUYA NOR FLASH, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P25D80SH-SSH-IT

PUYA · NOR FLASH · SOP-8

P25D80SH-SSH-IT from PUYA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip select input, which the datasheet lists as the device enable for serial transactions.
2 SO bidirectional Serial data output for 1 x I/O, and serial data input and output (SIO1) for 2 x I/O read mode.
3 WP# input Write protection, active low; hardware locking of protected sectors is controlled by this pin per the Overview.
4 GND power_in Ground of the device.
5 SI bidirectional Serial data input for 1 x I/O, and serial data input and output (SIO0) for 2 x I/O read mode.
6 SCLK input Serial interface clock input.
7 HOLD#/RESET# input Hardware reset pin, active low, or pauses the device without deselecting it.
8 VCC power_in Power supply of the device.

Key specifications

Parameter Value
Manufacturer PUYA
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operation temperature -40 85 °C 8
Storage temperature -65 150 °C 8
Maximum operation voltage 4 V 8
Voltage on any pin with respect to ground -0.6 4.1 V 8
DC output current 5 mA 8
Output capacitance COUT 8 pF VOUT=GND 8
Input capacitance CIN 6 pF VIN=GND 8
Deep power down current IDPD 0.5 5 uA CS#=Vcc, all other inputs at 0V or Vcc 9
Standby current ISB 10 20 uA CS#, HOLD#, WP#=VIH all inputs at CMOS levels 9
Read current (STR) (1, 2 IO) ICC1 5 8 mA f=85MHz; IOUT=0mA 9
Read current (STR) (1, 2 IO) ICC1 6 10 mA f=120MHz; IOUT=0mA 9
Program current ICC2 2 4 mA CS#=Vcc 9
Erase current ICC3 3 4 mA CS#=Vcc 9
Input load current ILI 2 uA All inputs at CMOS level 9
Output leakage ILO 2 uA All inputs at CMOS level 9
Output low voltage VOL 0.2 V IOL=100uA 9
Clock frequency for FREAD, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR fSCLK 120 MHz 10
Clock frequency for READ instructions fRSCLK 55 MHz 10
Clock frequency for 2READ, DREAD instructions fTSCLK 104 MHz 10
Clock high time tCH 3.7 ns 10
Clock low time tCL 3.7 ns 45% x (1/fSCLK) 10
Clock rise time (peak to peak) tCLCH 0.1 v/ns 10
Clock fall time (peak to peak) tCHCL 0.1 v/ns 10
CS# active setup time (relative to SCLK) tSLCH 5 ns 10
CS# not active hold time (relative to SCLK) tCHSL 5 ns 10
Data in setup time tDVCH 2 ns 10
Data in hold time tCHDX 3 ns 10
CS# active hold time (relative to SCLK) tCHSH 5 ns 10
CS# not active setup time (relative to SCLK) tSHCH 5 ns 10
CS# deselect time from read to next read tSHSL 20 ns 10
CS# deselect time from write, erase, program to read status register tSHSL 30 ns 10
Output disable time tSHQZ 6 ns 10
Clock low to output valid tCLQV 7 ns Loading 30pF 10
Clock low to output valid tCLQV 6 ns Loading 15pF 10
Output hold time tCLQX 0 ns 10
HOLD# active setup time (relative to SCLK) tHLCH 5 ns 10
HOLD# active hold time (relative to SCLK) tCHHH 5 ns 10
HOLD# not active setup time (relative to SCLK) tHHCH 5 ns 10
HOLD# not active hold time (relative to SCLK) tCHHL 5 ns 10
HOLD# to output low-Z tHHQX 6 ns 10
HOLD# to output high-Z tHLQZ 6 ns 10
Write protect setup time tWHSL 20 ns 10
Write protect hold time tSHWL 100 ns 10
CS# high to deep power-down mode tDP 3 us 10
CS# high to standby mode without electronic signature read tRES1 8 us 10
CS# high to standby mode with electronic signature read tRES2 8 us 10
Write status register cycle time tW 8 12 ms 10
Reset recovery time (for erase/program operation except WRSR) tReady 30 us 10
Reset recovery time (for WRSR operation) tReady 8 12 ms 10
Load memory page data to buffer time (256 byte) tBL 60 us 10
Load memory page data to buffer time (512 byte) tBL 120 us 10
Buffer clear to next instruction latency tBC 200 ns 10
Page program time (up to 256 bytes) tPP 1.5 3 ms 11
Page erase time tPE 16 30 ms 11
Sector erase time tSE 16 30 ms 11
Block erase time for 32K bytes tBE1 16 30 ms 11
Block erase time for 64K bytes tBE2 16 30 ms 11
Chip erase time tCE 80 180 ms 11

CAD (KiCad official)

  • Symbol: P25D80SH-SSH-IT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: p25d80sh-ssh-it-etched.step / p25d80sh-ssh-it-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p25d80sh-ssh-it.step / p25d80sh-ssh-it.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA datasheet (56 pp, sha256 cdae0238ef330908, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF