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P24CM01B-SSH-MIT

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PUYA EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P24CM01B-SSH-MIT

PUYA · EEPROM · SOP-8

P24CM01B-SSH-MIT from PUYA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No Connect; the datasheet assigns this pin no function.
2 E1 input Device address input for hardware addressing (up to four devices on one bus); if left floating it is internally pulled down to Vss.
3 E2 input Device address input for hardware addressing (up to four devices on one bus); if left floating it is internally pulled down to Vss.
4 Vss power_in Ground reference for the device.
5 SDA bidirectional Serial data input and output; open-drain driven and may be wire-OR'ed with other open-drain or open-collector devices, with the SDA pin normally pulled high by an external device.
6 SCL input Serial clock input; data is positive-edge clocked in and negative-edge clocked out.
7 WCB input Write control, active low: connecting WCB to VCC inhibits all write operations, connecting it to Vss allows normal writes, and if left floating it is internally pulled down to Vss.
8 VCC power_in Supply voltage, 1.7 V to 5.5 V per the DC characteristics (absolute maximum -0.5 V to 6.25 V).

Key specifications

Parameter Value
Manufacturer PUYA
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TSTG -65 150 °C 5
Ambient operating temperature TA -40 125 °C 5
Supply Voltage VCC -0.5 6.25 V 5
Input or output range VIO -0.5 6.25 V 5
DC output current IOL 5 mA SDA=0 5
Input/Output Capacitance (SDA) CI/O 8 pF VI/O= Vss 5
Input Capacitance (E1,E2,WCB,SCL) CIN 6 pF VIN= Vss 5
Supply Voltage VCC 1.7 5.5 V 5
Standby Current Isb 1 uA Vcc = 3.3V, TA = 85°C 5
Standby Current Isb 3 uA Vcc = 5.5V, TA = 85°C 5
Supply Current (read) ICC1 0.5 mA Vcc=5.5V, Read at 400Khz 5
Supply Current (write) ICC2 2.5 mA Vcc=5.5V, Write at 400Khz 5
Input Leakage Current ILI 0.1 1 µA VIN = VCC or Vss 5
Output Leakage Current ILO 0.05 1 µA VOUT = VCC or Vss 5
Input Low Level VIL -0.6 V 5
Output Low Level VCC = 1.7V (SDA) VOL1 0.2 V IOL = 1.5 mA 5
Output Low Level VCC = 3.0V (SDA) VOL2 0.4 V IOL = 2.1 mA 5
Clock Frequency, SCL fSCL 100 kHz 1.7≤VCC<5.5, CL=100pF 6
Clock Pulse Width Low tLOW 4.7 µs 1.7≤VCC<5.5, CL=100pF 6
Clock Pulse Width High tHIGH 4.7 µs 1.7≤VCC<5.5, CL=100pF 6
Clock Low to Data Out Valid tAA 3.45 µs 1.7≤VCC<5.5, CL=100pF 6
Noise Suppression Time tI 0.1 µs 1.7≤VCC<5.5, CL=100pF 6
Time the bus must be free before a new transmission can start tBUF 4.7 µs 1.7≤VCC<5.5, CL=100pF 6
Start Hold Time tHD.STA 4.7 µs 1.7≤VCC<5.5, CL=100pF 6
Start Setup Time tSU.STA 4 µs 1.7≤VCC<5.5, CL=100pF 6
Data In Hold Time tHD.DAT 0 µs 1.7≤VCC<5.5, CL=100pF 6
Data In Setup Time tSU.DAT 0 µs 1.7≤VCC<5.5, CL=100pF 6
Inputs Rise Time tR 1 µs 1.7≤VCC<5.5, CL=100pF 6
Inputs Fall Time tF 0.3 µs 1.7≤VCC<5.5, CL=100pF 6
Stop Setup Time tSU.STO 4 µs 1.7≤VCC<5.5, CL=100pF 6
Data Out Hold Time tDH 0.2 µs 1.7≤VCC<5.5, CL=100pF 6
WCB pin Setup Time tSU.WCB 4 µs 1.7≤VCC<5.5, CL=100pF 6
WCB pin Hold Time tHD.WCB 4 µs 1.7≤VCC<5.5, CL=100pF 6
Write Cycle Time tWR 5 ms 1.7≤VCC<5.5, CL=100pF 6
Clock Frequency, SCL fSCL 400 kHz 1.7≤VCC≤5.5, CL=100pF 6
Clock Pulse Width Low tLOW 1.3 µs 1.7≤VCC≤5.5, CL=100pF 6
Clock Pulse Width High tHIGH 0.6 µs 1.7≤VCC≤5.5, CL=100pF 6
Clock Low to Data Out Valid tAA 0.05 0.9 µs 1.7≤VCC≤5.5, CL=100pF 6
Time the bus must be free before a new transmission can start tBUF 1.3 µs 1.7≤VCC≤5.5, CL=100pF 6
Start Hold Time tHD.STA 0.6 µs 1.7≤VCC≤5.5, CL=100pF 6
Start Setup Time tSU.STA 0.6 µs 1.7≤VCC≤5.5, CL=100pF 6
Data In Setup Time tSU.DAT 0.1 µs 1.7≤VCC≤5.5, CL=100pF 6
Inputs Rise Time tR 0.3 µs 1.7≤VCC≤5.5, CL=100pF 6
Stop Setup Time tSU.STO 0.6 µs 1.7≤VCC≤5.5, CL=100pF 6
Data Out Hold Time tDH 0.05 µs 1.7≤VCC≤5.5, CL=100pF 6
WCB pin Setup Time tSU.WCB 1.2 µs 1.7≤VCC≤5.5, CL=100pF 6
WCB pin Hold Time tHD.WCB 1.2 µs 1.7≤VCC≤5.5, CL=100pF 6
Endurance EDR 1e+06 Write cycles 25°C, 3.3V, Page mode 7
Data retention DRET 100 Years 7

CAD (KiCad official)

  • Symbol: P24CM01B-SSH-MIT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: p24cm01b-ssh-mit-etched.step / p24cm01b-ssh-mit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p24cm01b-ssh-mit.step / p24cm01b-ssh-mit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA datasheet (21 pp, sha256 8e1243773bedcf45, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF