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P24C02A-TSH-MIR

Public Made by Adom

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PUYA EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P24C02A-TSH-MIR

PUYA · EEPROM · TSSOP-8

P24C02A-TSH-MIR from PUYA, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E0 input Device address bit 0 input that must match its hardwired level for the chip to respond, and it is internally pulled down to GND if left floating.
2 E1 input Device address bit 1 input that must match its hardwired level for the chip to respond, and it is internally pulled down to GND if left floating.
3 E2 input Device address bit 2 input that must match its hardwired level for the chip to respond, and it is internally pulled down to GND if left floating.
4 GND power_in Ground reference for the device.
5 SDA bidirectional Open-drain serial data input/output that may be wire-ORed with other open-drain or open-collector devices and is normally pulled high by an external resistor.
6 SCL input Serial clock input that clocks data in on the positive edge and clocks data out on the negative edge; the Schmitt-trigger input has a maximum fSCL of 400 kHz for 1.7 V ≤ VCC < 2.5 V and 1000 kHz for 2.5 V ≤ VCC ≤ 5.5 V.
7 WCB input Active-low write control: tying it to VCC inhibits all write operations, tying it to GND allows normal writes, and if left floating it is internally pulled down to GND (writes enabled).
8 VCC power_in Supply voltage; the -MI grade (this MPN) is specified for 1.7 V to 5.5 V with absolute maximum operating voltage of 6.25 V.

Key specifications

Parameter Value
Manufacturer PUYA
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage (P24C02A-MI) 1.7 5.5 V P24C02A-MI 4
Standby Current Isb 1 uA Vcc = 3.3V, TA = 85°C 4
Standby Current Isb 3 uA Vcc = 5.5V, TA = 85°C 4
Supply Current (read) ICC1 0.2 0.4 mA Vcc=5.5V, Read at 400Khz 4
Supply Current (write) ICC2 0.8 1.6 mA Vcc=5.5V Write at 400Khz 4
Input Leakage Current ILI 0.1 1 µA VIN = VCC or GND 4
Output Leakage Current ILO 0.05 1 µA VOUT = VCC or GND 4
Input Low Level VIL -0.6 V 4
Output Low Level (SDA) VOL1 0.2 V VCC = 1.7V (SDA), IOL = 1.5 mA 4
Output Low Level (SDA) VOL2 0.4 V VCC = 3.0V (SDA), IOL = 2.1 mA 4
Input / Output Capacitance (SDA) CI/O 8 pF VI/O=GND 4
Input Capacitance (E0, E1, E2, WCB, SCL) CIN 6 pF VIN=GND 4
Storage Temperature -65 150 °C 4
Operation Temperature -40 85 °C 4
Maximum Operation Voltage 6.25 V 4
Voltage on Any Pin with Respect to Ground -1 V 4
DC Output Current 5 mA 4
Clock Frequency, SCL fSCL 400 kHz 1.7≤VCC<2.5 5
Clock Frequency, SCL fSCL 1000 kHz 2.5≤VCC≤5.5 5
Clock Pulse Width Low tLOW 1.3 µs 1.7≤VCC<2.5 5
Clock Pulse Width Low tLOW 0.4 µs 2.5≤VCC≤5.5 5
Clock Pulse Width High tHIGH 0.6 µs 1.7≤VCC<2.5 5
Clock Pulse Width High tHIGH 0.4 µs 2.5≤VCC≤5.5 5
Clock Low to Data Out Valid tAA 0.05 0.9 µs 1.7≤VCC<2.5 5
Clock Low to Data Out Valid tAA 0.05 0.55 µs 2.5≤VCC≤5.5 5
Noise Suppression Time tI 0.1 µs 1.7≤VCC<2.5 5
Noise Suppression Time tI 0.05 µs 2.5≤VCC≤5.5 5
Time the bus must be free before a new transmission can start tBUF 1.3 µs 1.7≤VCC<2.5 5
Time the bus must be free before a new transmission can start tBUF 0.5 µs 2.5≤VCC≤5.5 5
Start Hold Time tHD.STA 0.6 µs 1.7≤VCC<2.5 5
Start Hold Time tHD.STA 0.25 µs 2.5≤VCC≤5.5 5
Start Setup Time tSU.STA 0.6 µs 1.7≤VCC<2.5 5
Start Setup Time tSU.STA 0.25 µs 2.5≤VCC≤5.5 5
Data In Hold Time tHD.DAT 0 µs 1.7≤VCC<2.5 5
Data In Setup Time tSU.DAT 0.1 µs 1.7≤VCC<2.5 5
Inputs Rise Time tR 0.3 µs 1.7≤VCC<2.5 5
Inputs Fall Time tF 0.3 µs 1.7≤VCC<2.5 5
Inputs Fall Time tF 0.1 µs 2.5≤VCC≤5.5 5
Stop Setup Time tSU.STO 0.6 µs 1.7≤VCC<2.5 5
Stop Setup Time tSU.STO 0.25 µs 2.5≤VCC≤5.5 5
Data Out Hold Time tDH 0.05 µs 1.7≤VCC<2.5 5
WCB pin Setup Time tSU.WCB 1.2 µs 1.7≤VCC<2.5 5
WCB pin Setup Time tSU.WCB 0.6 µs 2.5≤VCC≤5.5 5
WCB pin Hold Time tHD.WCB 1.2 µs 1.7≤VCC<2.5 5
WCB pin Hold Time tHD.WCB 0.6 µs 2.5≤VCC≤5.5 5
Write Cycle Time tWR 5 ms 1.7≤VCC<2.5 5

CAD (KiCad official)

  • Symbol: P24C02A-TSH-MIR
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: p24c02a-tsh-mir-etched.step / p24c02a-tsh-mir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p24c02a-tsh-mir.step / p24c02a-tsh-mir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA datasheet (20 pp, sha256 544fbedeccde1c1c, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF