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P24C02A-STH-MIR

Public Made by Adom

by adom

PUYA） EEPROM, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P24C02A-STH-MIR

PUYA） · EEPROM · SOT-23-5

P24C02A-STH-MIR from PUYA）, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCL input Serial clock input: data is clocked in on the positive edge and clocked out on the negative edge of SCL.
2 Vss power_in Ground, the reference for the VCC supply voltage.
3 SDA bidirectional Open-drain serial data pin for bidirectional transfer; it may be wire-OR'ed with other open-drain or open-collector devices.
4 WCB input Active-low write control: connecting WCB to VCC inhibits all memory writes, connecting it to Vss allows normal writes, and it is internally pulled down to Vss if left floating.
5 VCC power_in Supply voltage, specified from 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer PUYA）
Package SOT-23-5
Category Memory
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TSTG -65 150 °C 5
Ambient operating temperature TA -40 125 °C 5
Supply Voltage VCC -0.5 6.5 V 5
Input or output range VIO -0.5 6.5 V 5
DC output current (SDA=0) IOL 5 mA SDA=0 5
Input / Output Capacitance (SDA) CI/O 8 pF VI/O= Vss 5
Input Capacitance (E0, E1, E2, WCB, SCL) CIN 6 pF VIN= Vss 5
Supply Voltage Vcc 1.7 5.5 V 5
Standby Current Isb 1 uA Vcc = 3.3V 5
Standby Current Isb 3 uA Vcc = 5.5V 5
Supply Current (read) ICC1 0.2 0.4 mA Vcc=5.5V, Read at 400khz 5
Supply Current (write) ICC2 0.8 1.6 mA Vcc=5.5V, Write at 400khz 5
Input Leakage Current ILI 0.1 1 µA VIN = VCC or Vss 5
Output Leakage Current ILO 0.05 1 µA VOUT = VCC or Vss 5
Input Low Level VIL -0.5 V 5
Output Low Level (SDA) VOL1 0.2 V VCC = 1.7V (SDA), IOL = 0.15 mA 5
Output Low Level (SDA) VOL2 0.4 V VCC = 3.0V (SDA), IOL = 2.1 mA 5
VCC voltage needed to go below VPWD for ensuring initialization VPWD 0.7 V 9
Minimum duration for ensuring initialization tPWD 300 us 9
VCC(min.) to device operation tVSL 70 us 9
VCC Rise Time tVR 1 500000 us/V 9
Clock Frequency, SCL (100kHz table) fSCL 100 kHz 6
Clock Pulse Width Low (100kHz table) tLOW 4.7 µs 6
Clock Pulse Width High (100kHz table) tHIGH 4 µs 6
Clock Low to Data Out Valid (100kHz table) tAA 0.05 3.45 µs 6
Noise Suppression Time (100kHz table) tI 0.1 µs 6
Bus free time before new transmission (100kHz table) tBUF 4.7 µs 6
Start Hold Time (100kHz table) tHD.STA 4 µs 6
Start Setup Time (100kHz table) tSU.STA 4.7 µs 6
Data In Hold Time (100kHz table) tHD.DAT 0 µs 6
Data In Setup Time (100kHz table) tSU.DAT 0.25 µs 6
Inputs Rise Time (100kHz table) tR 1 µs 6
Inputs Fall Time (100kHz table) tF 0.3 µs 6
Stop Setup Time (100kHz table) tSU.STO 4 µs 6
Data Out Hold Time (100kHz table) tDH 0.05 µs 6
WCB pin Setup Time (100kHz table) tSU.WCB 4 µs 6
Write Cycle Time (100kHz table) tWR 5 ms 7
Clock Frequency, SCL (first column group) fSCL 400 kHz 6
Clock Pulse Width Low (first column group) tLOW 1.3 µs 6
Clock Pulse Width High (first column group) tHIGH 0.6 µs 6
Clock Low to Data Out Valid (first column group) tAA 0.05 0.9 µs 6
Noise Suppression Time (first column group) tI 0.1 µs 6
Bus free time before new transmission (first column group) tBUF 1.3 µs 6
Start Hold Time (first column group) tHD.STA 0.6 µs 6
Start Setup Time (first column group) tSU.STA 0.6 µs 6
Data In Hold Time (first column group) tHD.DAT 0 µs 6
Data In Setup Time (first column group) tSU.DAT 0.1 µs 6
Inputs Rise Time (first column group) tR 0.3 µs 6
Inputs Fall Time (first column group) tF 0.3 µs 6
Stop Setup Time (first column group) tSU.STO 0.6 µs 6
Data Out Hold Time (first column group) tDH 0.05 µs 6
WCB pin Setup Time (first column group) tSU.WCB 1.2 µs 6
WCB pin Hold Time (first column group) tHD.WCB 1.2 µs 7
Write Cycle Time (first column group) tWR 5 ms 7
Clock Frequency, SCL (second column group) fSCL 1000 kHz 6
Clock Pulse Width Low (second column group) tLOW 0.4 µs 6
Clock Pulse Width High (second column group) tHIGH 0.4 µs 6
Clock Low to Data Out Valid (second column group) tAA 0.05 0.55 µs 6
Noise Suppression Time (second column group) tI 0.05 µs 6
Bus free time before new transmission (second column group) tBUF 0.5 µs 6
Start Hold Time (second column group) tHD.STA 0.25 µs 6
Start Setup Time (second column group) tSU.STA 0.25 µs 6
Data In Hold Time (second column group) tHD.DAT 0 µs 6
Data In Setup Time (second column group) tSU.DAT 0.1 µs 6
Inputs Rise Time (second column group) tR 0.3 µs 6
Inputs Fall Time (second column group) tF 0.1 µs 6
Stop Setup Time (second column group) tSU.STO 0.25 µs 6
Data Out Hold Time (second column group) tDH 0.05 µs 6
WCB pin Setup Time (second column group) tSU.WCB 0.6 µs 6
WCB pin Hold Time (second column group) tHD.WCB 0.6 µs 7
Write Cycle Time (second column group) tWR 5 ms 7

CAD (KiCad official)

  • Symbol: P24C02A-STH-MIR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: p24c02a-sth-mir-etched.step / p24c02a-sth-mir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p24c02a-sth-mir.step / p24c02a-sth-mir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA） datasheet (25 pp, sha256 049ce4cb42b67165, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF