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OPA928DR

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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OPA928DR

Texas Instruments · Operational Amplifier · SOIC-8

OPA928DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN+ input Noninverting input; it is the input the internal guard buffer follows to keep the input differential voltage near zero.
2 GRD output Guard buffer pin; the guard buffer output is accessed here to drive guard copper around high-impedance input traces, and it is isolated from large capacitive loads by a nominal 1kΩ resistor.
3 DNC unconnected Do not connect; leave floating.
4 V- power_in Negative (lowest) power supply pin; the supply is specified from 4.5V to 36V single supply or ±2.25V to ±18V dual supply.
5 V+ power_in Positive (highest) power supply pin; the supply is specified from 4.5V to 36V single supply or ±2.25V to ±18V dual supply.
6 OUT output Amplifier output.
7 GRD output Guard buffer pin; the guard buffer output is accessed here to drive guard copper around high-impedance input traces, and it is isolated from large capacitive loads by a nominal 1kΩ resistor.
8 IN- input Inverting input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, dual supply (absolute maximum) VS -20 20 V Dual supply 3
Supply voltage, single supply (absolute maximum) VS 40 V Single supply 3
Signal input pin voltage, common-mode -0.5 0.5 V Common-mode; printed as (V-), 0.5 V (min) and (V+) + 0.5 V (max) 3
Signal input pin voltage, differential -0.5 0.5 V Differential 3
Signal input pin current -10 10 mA 3
Guard pin to signal input pin voltage -0.5 0.5 V 3
Junction temperature TJ 150 °C 3
Storage temperature Tstg -65 150 °C 3
Supply voltage, dual supply (recommended) VS 2.25 18 V Dual supply; printed ±2.25 V (min) and ±18 V (max) 3
Supply voltage, single supply (recommended) VS 4.5 36 V Single supply 3
Ambient temperature (recommended) TA -40 125 °C 3
Input bias current IB -20 1 20 fA 4.5V ≤ VS < 8V; RH < 50% 4
Input bias current IB -20 20 fA 4.5V ≤ VS < 8V; TA = -40°C to +85°C 4
Input offset current IOS -20 1 20 fA 4.5V ≤ VS < 8V; RH < 50% 4
Input offset voltage VOS -25 5 25 µV 4.5V ≤ VS < 8V 4
Input offset voltage VOS -105 20 105 µV 4.5V ≤ VS < 8V; TA = -40°C to +125°C 4
Input offset voltage drift dVOS/dT -0.8 0.1 0.8 µV/°C 4.5V ≤ VS < 8V; TA = -40°C to +125°C 4
Power-supply rejection ratio PSRR -1 0.3 1 µV/V 4.5V < VS < 36V, VCM = VS/2, 0.75V; TA = -40°C to +125°C 4
Common-mode rejection ratio CMRR 96 120 dB 4.5V ≤ VS < 8V; (V-), 0.1V < VCM < (V+), 3V 4
Open-loop voltage gain AOL 110 120 dB 4.5V ≤ VS < 8V; (V-) + 0.6V < VO < (V+), 0.6V, RL = 2kΩ 4
Voltage output swing from rail VO 200 500 mV 4.5V ≤ VS < 8V; RL = 2kΩ 5
Short-circuit current ISC -30 30 mA 4.5V ≤ VS < 8V 5
Quiescent current IQ 275 400 µA 4.5V ≤ VS < 8V; IO = 0A 5
Guard buffer input offset voltage VOSG -50 8 50 µV 4.5V ≤ VS < 8V; (V-) + 0.1V < VCM < (V+), 3V 5
Guard buffer output swing from rail VOGB 5 15 mV 4.5V ≤ VS < 8V; No load 5
Input bias current IB -20 1 20 fA 8V ≤ VS ≤ 16V; RH < 50% 6
Input bias current IB -20 20 fA 8V ≤ VS ≤ 16V; TA = -40°C to +85°C 6
Input offset current IOS -20 1 20 fA 8V ≤ VS ≤ 16V; RH < 50% 6
Input offset voltage VOS -25 5 25 µV 8V ≤ VS ≤ 16V 6
Input offset voltage VOS -105 20 105 µV 8V ≤ VS ≤ 16V; TA = -40°C to +125°C 6
Input offset voltage drift dVOS/dT -0.8 0.1 0.8 µV/°C 8V ≤ VS ≤ 16V; TA = -40°C to +125°C 6
Power-supply rejection ratio PSRR -1 0.3 1 µV/V 4.5V < VS < 36V, VCM = VS/2, 0.75V; TA = -40°C to +125°C 6
Common-mode rejection ratio CMRR 108 124 dB 8V ≤ VS ≤ 16V; (V-), 0.1V < VCM < (V+), 3V 6
Open-loop voltage gain AOL 116 132 dB 8V ≤ VS ≤ 16V; (V-) + 0.6V < VO < (V+), 0.6V, RL = 2kΩ 6
Voltage output swing from rail VO 200 500 mV 8V ≤ VS ≤ 16V; RL = 2kΩ 7
Short-circuit current ISC -65 65 mA VS = 16V 7
Quiescent current IQ 275 400 µA 8V ≤ VS ≤ 16V; IO = 0A 7
Guard buffer input offset voltage VOSG -50 8 50 µV 8V ≤ VS ≤ 16V; (V-) + 0.1V < VCM < (V+), 3V 7
Guard buffer output swing from rail VOG 5 15 mV 8V ≤ VS ≤ 16V; No load 7
Input bias current IB -75 1 75 fA 16V < VS ≤ 36V; RH < 50% 8
Input bias current IB -75 75 fA 16V < VS ≤ 36V; TA = -40°C to +85°C 8
Input offset current IOS -75 1 75 fA 16V < VS ≤ 36V; RH < 50% 8
Input offset voltage VOS -25 5 25 µV 16V < VS ≤ 36V 8
Input offset voltage VOS -105 20 105 µV 16V < VS ≤ 36V; TA = -40°C to +125°C 8
Input offset voltage drift dVOS/dT -0.8 0.1 0.8 µV/°C 16V < VS ≤ 36V; TA = -40°C to +125°C 8
Power-supply rejection ratio PSRR -1 0.3 1 µV/V 4.5V < VS < 36V, VCM = VS/2, 0.75V; TA = -40°C to +125°C 8
Common-mode rejection ratio CMRR 114 130 dB 16V < VS ≤ 36V; (V-), 0.1V < VCM < (V+), 3V 8
Open-loop voltage gain AOL 124 138 dB 16V < VS ≤ 36V; (V-) + 1V < VO < (V+), 1V, RL = 2kΩ 8
Voltage output swing from rail VO 0.5 1 V 16V < VS ≤ 36V; RL = 2kΩ 9
Short-circuit current ISC -65 65 mA VS = 36V 9
Quiescent current IQ 275 400 µA 16V < VS ≤ 36V; IO = 0A 9
Guard buffer input offset voltage VOSGB -50 8 50 µV 16V < VS ≤ 36V 9
Guard buffer output swing from rail VOGB 5 15 mV 16V < VS ≤ 36V; No load 9
Junction-to-ambient thermal resistance RθJA 113.9 °C/W 3
Junction-to-case(top) thermal resistance RθJC(top) 51.4 °C/W 3
Junction-to-board thermal resistance RθJB 58 °C/W 3
Junction-to-top characterization parameter ψJT 9 °C/W 3
Junction-to-board characterization parameter ψJB 57.1 °C/W 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper high-performance internal guard buffer that can be accessed at pin 2 and pin 7 to drive the PCB guard copper; 28

CAD (KiCad official)

  • Symbol: OPA928DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: opa928dr-etched.step / opa928dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); opa928dr.step / opa928dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (50 pp, sha256 06ab87dcd0ffd4d3, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF