Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

OPA392DBVR

Texas Instruments · Pre-ordered Products · SOT-23-5

OPA392DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Amplifier output with rail-to-rail swing and +65mA/-55mA short-circuit current capability.
2 V- power_in Negative (lowest) power supply; single-supply operation is 1.7 V to 5.5 V.
3 +IN input Noninverting input of the amplifier, rail-to-rail with common-mode range of (V-) - 0.5 V to (V+) + 0.5 V absolute maximum.
4 -IN input Inverting input of the amplifier, rail-to-rail with common-mode range of (V-) - 0.5 V to (V+) + 0.5 V absolute maximum.
5 V+ power_in Positive (highest) power supply; single-supply operation is 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Solders / Accessories / Batteries
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS 6 V Single-supply 6
Supply voltage dual VS 3 V Dual-supply (±) 6
Common-mode input voltage -0.5 0.5 V (V-), 0.5 to (V+) + 0.5, relative to rails 6
Differential input voltage 0.2 V (V+), (V-) + 0.2 6
Input current, all pins -10 10 mA 6
Operating temperature TA -55 150 °C 6
Junction temperature TJ -55 150 °C 6
Storage temperature Tstg -65 150 °C 6
ESD HBM V(ESD) -2000 2000 V Human-body model, ANSI/ESDA/JEDEC JS-001 6
ESD CDM V(ESD) -500 500 V Charged device model, JS-002 6
Supply voltage single-supply VS 1.7 5.5 V Single-supply 6
Supply voltage dual-supply VS -0.85 2.75 V Dual-supply, ±0.85 to ±2.75 6
Specified temperature TA -40 125 °C 6
Junction-to-ambient thermal resistance RθJA 187.1 °C/W DBV (SOT-23), 5 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 107.4 °C/W DBV (SOT-23), 5 pins 7
Junction-to-board thermal resistance RθJB 57.5 °C/W DBV (SOT-23), 5 pins 7
Junction-to-top characterization parameter ΨJT 33.5 °C/W DBV (SOT-23), 5 pins 7
Junction-to-board characterization parameter ΨJB 57.1 °C/W DBV (SOT-23), 5 pins 7
Input offset voltage VOS -10 1 10 μV VS = 5.0 V 8
Input offset voltage VOS -30 2 30 μV VS = 5.0 V, VCM = (V+), 200 mV 8
Input offset voltage over temperature VOS -100 100 μV VS = 5.0 V, TA = -40°C to +125°C 8
Input offset voltage over temperature, VCM = V- VOS -125 125 μV VCM = V-, TA = -40°C to +125°C 8
Input offset voltage drift dVOS/dT 0.16 μV/°C VS = 5.0 V, TA = 0°C to 85°C 8
Input offset voltage drift dVOS/dT 0.6 μV/°C VS = 5.0 V, TA = -40°C to +125°C 8
Input offset voltage drift dVOS/dT 0.18 0.9 μV/°C VCM = 5.0 V, TA = -40°C to +125°C 8
Power supply rejection ratio PSRR -30 30 μV/V VCM = V- 8
Power supply rejection ratio over temperature PSRR -80 80 μV/V TA = -40°C to +125°C 8
Input bias current IB -0.8 0.01 0.8 pA 8
Input bias current IB -5 5 pA TA = -40°C to +85°C 8
Input bias current IB -30 30 pA TA = -40°C to +125°C 8
Input offset current IOS -0.8 0.01 0.8 pA 8
Input offset current IOS -5 5 pA TA = -40°C to +85°C 8
Input offset current IOS -30 30 pA TA = -40°C to +125°C 8
Input voltage noise 2 3.2 μVPP f = 0.1 Hz to 10 Hz; max at VCM = (V+), 0.3 8
Input voltage noise density eN 6.5 10.4 nV/√Hz f = 1 kHz; max at VCM = (V+), 0.3 8
Input voltage noise density eN 4.4 5.8 nV/√Hz f = 10 kHz; max at VCM = (V+), 0.3 8
Input current noise density iN 70 fA/√Hz f = 1 kHz, OPA392DBV 8
Common-mode rejection ratio CMRR 75 120 dB (V-) < VCM < (V+), 1.5 V 8
Common-mode rejection ratio CMRR 113 dB TA = -40°C to +125°C 8
Common-mode rejection ratio CMRR 66 97 dB (V-) < VCM < (V+), TA = -40°C to +125°C 8
Common-mode rejection ratio CMRR 88 111 dB VS = 5.5 V 8
Open-loop voltage gain AOL 115 132 dB VS = 5.5 V, (V-) + 50 mV < VOUT < (V+), 50 mV 9
Open-loop voltage gain AOL 110 128 dB VS = 5.5 V, (V-) + 100 mV < VO < (V+), 100 mV, RL = 2 kΩ 9
Open-loop voltage gain AOL 100 dB VS = 5.5 V, RL = 2 kΩ, TA = -40°C to +125°C 9
Open-loop voltage gain AOL 106 124 dB VS = 1.7 V, (V-) + 50 mV < VOUT < (V+), 50 mV, VCM = (V+), 1.15 V 9
Gain-bandwidth product GBW 13 MHz AV = 1000 V/V 9
Slew rate falling SR 4.5 V/μs 4-V step, gain = +1, falling 9
Slew rate rising SR 3.5 V/μs 4-V step, gain = +1, rising 9
Phase margin 45 ° CL = 100 pF, OPA392DBV 9
Settling time tS 0.75 μs To 0.1%, 2-V step, gain = +1 9
Settling time tS 1 μs To 0.01%, 2-V step, gain = +1 9
Overload recovery time 0.45 μs VIN × gain > VS 9
Short-circuit current sinking ISC -55 mA Sinking, VS = 5.5 V 9
Short-circuit current sourcing ISC 65 mA Sourcing, VS = 5.5 V 9
Quiescent current per amplifier IQ 1.22 1.4 mA IO = 0 mA 9
Quiescent current per amplifier over temperature IQ 1.5 mA IO = 0 mA, TA = -40°C to +125°C 9

CAD (KiCad official)

  • Symbol: OPA392DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: opa392dbvr-etched.step / opa392dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); opa392dbvr.step / opa392dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (61 pp, sha256 9d044fdab5a980c4, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF