component
OPA2132U
Public Made by Adomby adom
Texas Instruments FET InputAmplifiers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownOPA2132U
Texas Instruments · FET InputAmplifiers · SOIC-8
OPA2132U from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT A | output | Output of channel A. |
| 2 | -IN A | input | Inverting input of channel A. |
| 3 | +IN A | input | Noninverting input of channel A. |
| 4 | V- | power_in | Negative (lowest) power supply. |
| 5 | +IN B | input | Noninverting input of channel B. |
| 6 | -IN B | input | Inverting input of channel B. |
| 7 | OUT B | output | Output of channel B. |
| 8 | V+ | power_in | Positive (highest) power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VOS | -0.5 | 0.2 | 0.5 | mV | 7 | |
| Input offset voltage drift | dVOS/dT | -10 | 2 | 10 | μV/°C | TA = -40°C to +85°C | 7 |
| Power-supply rejection ratio | PSRR | -15 | 5 | 15 | μV/V | ±2.5V ≤ VS ≤ ±18V | 7 |
| Input bias current | IB | -50 | 5 | 50 | pA | 7 | |
| Input offset current | IOS | -50 | 2 | 50 | pA | 7 | |
| Common-mode rejection ratio | CMRR | 96 | 100 | dB | -12.5V ≤ VCM ≤ 11.5V | 7 | |
| Open-loop voltage gain | AOL | 110 | 120 | dB | RL = 10kΩ, -14.5V ≤ VO ≤ 13.8V | 7 | |
| Open-loop voltage gain | AOL | 110 | 126 | dB | RL = 2kΩ, -13.8V ≤ VO ≤ 13.5V | 7 | |
| Open-loop voltage gain | AOL | 110 | 130 | dB | RL = 600Ω, -12.8V ≤ VO ≤ 12.5V | 7 | |
| Quiescent current (per amplifier) | IQ | -4.8 | 4 | 4.8 | mA | IO = 0mA | 7 |
| Supply voltage, (V+), (V-) | VS | 36 | V | 5 | |||
| Input current | II | -10 | 10 | mA | 5 | ||
| Operating temperature | TA | -40 | 125 | °C | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | Tstg | -55 | 125 | °C | 5 | ||
| Supply voltage, dual supply | VS | 2.5 | 15 | 18 | V | Dual supply | 5 |
| Supply voltage, single supply | VS | 9 | 30 | 36 | V | Single supply | 5 |
| Ambient temperature | TA | -40 | 85 | °C | 5 | ||
| Junction-to-ambient thermal resistance (D SOIC, 8 pins) | RθJA | 160 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (D SOIC, 8 pins) | RθJC(top) | 75 | °C/W | 6 | |||
| Junction-to-board thermal resistance (D SOIC, 8 pins) | RθJB | 60 | °C/W | 6 | |||
| Junction-to-top characterization parameter (D SOIC, 8 pins) | ΨJT | 9 | °C/W | 6 | |||
| Junction-to-board characterization parameter (D SOIC, 8 pins) | ΨJB | 50 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
OPA2132U - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
opa2132u-etched.step/opa2132u-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);opa2132u.step/opa2132u.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
8c5a1244bd0b3579, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).