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OPA210IDT

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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OPA210IDT

Texas Instruments · Operational Amplifier · SOIC-8

OPA210IDT from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 -IN input Inverting input; signal input pins must stay between (V-) - 0.5 V and (V+) + 0.5 V, with input current limited to ±10 mA.
3 +IN input Noninverting input; signal input pins must stay between (V-) - 0.5 V and (V+) + 0.5 V, with input current limited to ±10 mA.
4 V- power_in Negative (lowest) power supply; specified supply range is ±2.25 V to ±18 V, and total supply (V+) - (V-) must not exceed 40 V.
5 NC unconnected No internal connection.
6 OUT output Amplifier output; short circuit to ground is continuous (one amplifier per package).
7 V+ power_in Positive (highest) power supply; specified supply range is ±2.25 V to ±18 V, and total supply (V+) - (V-) must not exceed 40 V.
8 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VS 40 V VS = (V+) – (V–) 4
Signal input pins voltage -0.5 0.5 V Rail-relative: min (V–) – 0.5 V, max (V+) + 0.5 V 4
Signal input pins differential voltage 1 V Differential 4
Signal input pins current -10 10 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, human-body model (HBM) V(ESD) -4000 4000 V Per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged-device model (CDM) V(ESD) -1500 1500 V Per JEDEC JESD22-C101 4
Specified voltage VS 2.25 18 V Supply range ±2.25 V to ±18 V 4
Specified temperature -40 125 °C 4
Operating temperature TA -55 150 °C 4
Input offset voltage VOS -35 5 35 µV VS = ±15 V, VCM = 0 V 6
Common-mode voltage range VCM 1.5 -1.5 V Rail-relative offsets: min = (V–) + 1.5 V, max = (V+) – 1.5 V; ±15 V table 6
Input offset voltage drift dVOS/dT -0.5 0.1 0.5 µV/°C TA = –40°C to 125°C 6
Input offset voltage matching VOS -35 5 35 µV 6
PSRR vs power supply PSRR 0.05 0.5 µV/V VS = ±2.25 V to ±18 V, TA = 25°C 6
PSRR vs power supply PSRR -1 1 µV/V VS = ±2.25 V to ±18 V, TA = –40°C to 125°C 6
Input bias current IB -2 0.3 2 nA VCM = 0 V, TA = 25°C 6
Input bias current IB -4 4 nA VCM = 0 V, TA = –40°C to 85°C 6
Input bias current IB -7 7 nA VCM = 0 V, TA = –40°C to 125°C 6
Input offset current IOS -2 0.1 2 nA VCM = 0 V, TA = 25°C 6
Input offset current IOS -4 4 nA VCM = 0 V, TA = –40°C to 85°C 6
Input offset current IOS -7 7 nA VCM = 0 V, TA = –40°C to 125°C 6
Common-mode rejection ratio CMRR 132 140 dB (V–) + 1.5 V < VCM < (V+) – 1.5 V 6
Common-mode rejection ratio CMRR 120 130 dB (V–) + 1.5 V < VCM < (V+) – 1.5 V, TA = –40°C to 125°C 6
Open-loop voltage gain AOL 126 132 dB (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ, TA = 25°C 6
Open-loop voltage gain AOL 120 dB (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ, TA = –40°C to 125°C 6
Open-loop voltage gain AOL 114 120 dB (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω, TA = 25°C 6
Open-loop voltage gain AOL 110 dB (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω, TA = –40°C to 85°C 6
Voltage output swing 0.2 -0.2 V Rail-relative offsets: min (V–) + 0.2 V, max (V+) – 0.2 V; RL = 10 kΩ, AOL > 130 dB 7
Voltage output swing 0.6 -0.6 V Rail-relative offsets: min (V–) + 0.6 V, max (V+) – 0.6 V; RL = 600 Ω, AOL > 114 dB 7
Short-circuit current ISC -65 65 mA VS = ±18 V 7
Quiescent current (per amplifier) IQ 2.2 2.5 mA IO = 0 A, TA = 25°C 7
Quiescent current (per amplifier) IQ 3.25 mA IO = 0 A, TA = –40°C to 125°C 7
Junction-to-ambient thermal resistance (D, SOIC 8-pin) RθJA 131.2 °C/W OPA210 D (SOIC) 8-pin package 5
Junction-to-case (top) thermal resistance (D, SOIC 8-pin) RθJC(top) 71.6 °C/W OPA210 D (SOIC) 8-pin package 5
Junction-to-board thermal resistance (D, SOIC 8-pin) RθJB 74.6 °C/W OPA210 D (SOIC) 8-pin package 5
Junction-to-top characterization parameter (D, SOIC 8-pin) ψJT 22.4 °C/W OPA210 D (SOIC) 8-pin package 5
Junction-to-board characterization parameter (D, SOIC 8-pin) ψJB 73.8 °C/W OPA210 D (SOIC) 8-pin package 5

CAD (KiCad official)

  • Symbol: OPA210IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: opa210idt-etched.step / opa210idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); opa210idt.step / opa210idt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 a2f541422f64a282, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF