# OPA1652AIDR

**Texas Instruments** · Precision OpAmps · SOIC-8

OPA1652AIDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT A | output | Channel A amplifier output. Rail-to-rail output stage, swings to within 800 mV of the supply rails with a 2 kΩ load; short-circuit current ±50 mA. |
| 2 | -IN A | input | Channel A inverting input. FET input, typical bias current 10 pA. Common-mode range (V−)+0.5 V to (V+)−2 V. |
| 3 | +IN A | input | Channel A non-inverting input. FET input, typical bias current 10 pA. Common-mode range (V−)+0.5 V to (V+)−2 V. |
| 4 | V- | power_in | Negative supply rail. Use −(VS/2) for split supplies or GND for single-supply operation. Total supply (V+)−(V−) range 4.5 V to 36 V (abs. max 40 V). |
| 5 | +IN B | input | Channel B non-inverting input. FET input, typical bias current 10 pA. Common-mode range (V−)+0.5 V to (V+)−2 V. |
| 6 | -IN B | input | Channel B inverting input. FET input, typical bias current 10 pA. Common-mode range (V−)+0.5 V to (V+)−2 V. |
| 7 | OUT B | output | Channel B amplifier output. Rail-to-rail output stage, swings to within 800 mV of the supply rails with a 2 kΩ load; short-circuit current ±50 mA. |
| 8 | V+ | power_in | Positive supply rail. Total supply (V+)−(V−) range 4.5 V to 36 V (abs. max 40 V). Bypass with a local decoupling capacitor to V−. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `OPA1652AIDR`
- `OPA1652AIDRIDGKR`
- `OPA1652AIDRIDGK`
- `OPA1652AIDRIPWR`
- `OPA1652AIDRIPW`

## CAD (KiCad official)

- Symbol: `OPA1652AIDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `opa1652aidr-etched.step` / `opa1652aidr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `opa1652aidr.step` / `opa1652aidr.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`opa1652aidr.step`](opa1652aidr.step) | 122 KB | You want the bare part, or you mark your own boards. |
| [`opa1652aidr-etched.step`](opa1652aidr-etched.step) | 2.1 MB | You want the part with `OPA1652AIDR` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 535 faces against 147 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/opa1652a.pdf) (29 pp, sha256 `625e72eb505829b8`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/opa1652aidr-datasheet.pdf)