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OP177GSZ

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Analog Devices Precision Op Amps, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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OP177GSZ

Analog Devices · Precision Op Amps · SOIC-8

OP177GSZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOS TRIM passive Optional offset null terminal; a 20 kΩ potentiometer between pins 1 and 8 with its wiper to V- gives a typical ±3 mV trim range.
2 -IN input Inverting input of the amplifier; absolute maximum input voltage ±22 V and differential input ±30 V.
3 +IN input Noninverting input of the amplifier; absolute maximum input voltage ±22 V and differential input ±30 V.
4 V- power_in Negative supply voltage; absolute maximum supply voltage ±22 V.
5 NC unconnected No connect; not internally connected.
6 OUT output Amplifier output with ±13.5 V typical swing into RL ≥ 10 kΩ and indefinite short-circuit duration.
7 V+ power_in Positive supply voltage; absolute maximum supply voltage ±22 V.
8 VOS TRIM passive Optional offset null terminal; a 20 kΩ potentiometer between pins 1 and 8 with its wiper to V- gives a typical ±3 mV trim range.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VOS 20 60 μV VS = ±15 V, TA = 25°C 3
Input offset current IOS 0.3 2.8 nA VS = ±15 V, TA = 25°C 3
Input bias current IB -0.2 1.2 2.8 nA VS = ±15 V, TA = 25°C 3
Input noise voltage en 118 150 nV rms fO = 1 Hz to 100 Hz 3
Input noise current in 3 8 pA rms fO = 1 Hz to 100 Hz 3
Input resistance, differential mode RIN 18.5 45 MΩ Differential mode 3
Input resistance, common mode RINCM 200 GΩ 3
Input voltage range IVR -13 14 V 3
Common-mode rejection ratio CMRR 115 140 dB VCM = ±13 V 3
Power supply rejection ratio PSRR 110 120 dB VS = ±3 V to ±18 V 3
Large signal voltage gain AVO 2000 6000 V/mV RL ≥ 2 kΩ, VO = ±10 V 3
Output voltage swing VO -13.5 14 V RL ≥ 10 kΩ 3
Output voltage swing VO -12.5 13 V RL ≥ 2 kΩ 3
Output voltage swing VO -12 12.5 V RL ≥ 1 kΩ 3
Slew rate SR 0.1 0.3 V/μs RL ≥ 2 kΩ 3
Closed-loop bandwidth BW 0.4 0.6 MHz AVCL = 1 3
Open-loop output resistance RO 60 Ω 3
Power consumption PD 50 60 mW VS = ±15 V, no load 3
Power consumption PD 3.5 4.5 mW VS = ±3 V, no load 3
Supply current ISY 1.6 2 mA VS = ±15 V, no load 3
Offset adjustment range -3 3 mV RP = 20 kΩ 3
Input offset voltage VOS 20 100 μV −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Average input offset voltage drift TCVOS 0.7 1.2 μV/°C −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Input offset current IOS 0.5 4.5 nA −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Average input offset current drift TCIOS 1.5 85 pA/°C −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Input bias current IB -6 2.4 6 nA −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Average input bias current drift TCIB 15 60 pA/°C −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Input voltage range IVR -13 13.5 V −40°C ≤ TA ≤ +85°C, VS = ±15 V 4
Common-mode rejection ratio CMRR 110 140 dB −40°C ≤ TA ≤ +85°C, VCM = ±13 V 4
Power supply rejection ratio PSRR 106 115 dB −40°C ≤ TA ≤ +85°C, VS = ±3 V to ±18 V 4
Large-signal voltage gain AVO 1000 4000 V/mV −40°C ≤ TA ≤ +85°C, RL ≥ 2 kΩ, VO = ±10 V 4
Output voltage swing VO -12 13 V −40°C ≤ TA ≤ +85°C, RL ≥ 2 kΩ 4
Power consumption PD 60 75 mW −40°C ≤ TA ≤ +85°C, VS = ±15 V, no load 4
Supply current ISY 2 2.5 mA −40°C ≤ TA ≤ +85°C, VS = ±15 V, no load 4
Supply voltage -22 22 V 5
Internal power dissipation 500 mW 5
Differential input voltage -30 30 V 5
Input voltage -22 22 V 5
Storage temperature range -65 125 °C 5
Operating temperature range -40 85 °C 5
Lead temperature 300 °C Soldering, 60 sec 5
DICE junction temperature TJ -65 150 °C 5
Thermal resistance, junction-to-ambient, 8-lead SOIC θJA 158 °C/W Device soldered to printed circuit board (worst-case mounting) 5
Thermal resistance, junction-to-case, 8-lead SOIC θJC 43 °C/W 5

CAD (KiCad official)

  • Symbol: OP177GSZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: op177gsz-etched.step / op177gsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); op177gsz.step / op177gsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 5a5ff145b727a9a8, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF