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OP177GSZ-REEL

Analog Devices · Precision Op Amps · SOIC-8

OP177GSZ-REEL from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOS TRIM	passive	Offset null pin; a 20 kΩ potentiometer between the two VOS TRIM pins with wiper to V+ gives a typical ±3 mV adjustment range (optional).
2	-IN	input	Inverting input of the amplifier.
3	+IN	input	Noninverting input of the amplifier.
4	V-	power_in	Negative supply; absolute maximum supply voltage is ±22 V.
5	NC	unconnected	No connect; not internally connected.
6	OUT	output	Amplifier output with ±13.5 V typical swing (RL ≥ 10 kΩ) and indefinite short-circuit duration.
7	V+	power_in	Positive supply; absolute maximum supply voltage is ±22 V.
8	VOS TRIM	passive	Offset null pin; used with pin 1 and a 20 kΩ potentiometer for optional offset adjustment of about ±3 mV.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-8
Category	Amplifiers/Comparators
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Offset Voltage	VOS		20	60	μV	VS = ±15 V, TA = 25°C (table 1 header)	3
Input Offset Current	IOS		0.3	2.8	nA	VS = ±15 V, TA = 25°C (table 1 header)	3
Input Bias Current	IB	-0.2	1.2	2.8	nA	VS = ±15 V, TA = 25°C (table 1 header)	3
Input Noise Voltage	en		118	150	nV rms	fO = 1 Hz to 100 Hz	3
Input Noise Current	in		3	8	pA rms	fO = 1 Hz to 100 Hz	3
Common-Mode Rejection Ratio	CMRR	115	140		dB	VCM = ±13 V	3
Power Supply Rejection Ratio	PSRR	110	120		dB	VS = ±3 V to ±18 V	3
Large Signal Voltage Gain	AVO	2000	6000		V/mV	RL ≥ 2 kΩ, VO = ±10 V	3
Output Voltage Swing (RL ≥ 10 kΩ)	VO	-13.5	14	13.5	V	RL ≥ 10 kΩ	3
Output Voltage Swing (RL ≥ 2 kΩ)	VO	-12.5	13	12.5	V	RL ≥ 2 kΩ	3
Output Voltage Swing (RL ≥ 1 kΩ)	VO	-12	12.5	12	V	RL ≥ 1 kΩ	3
Slew Rate	SR	0.1	0.3		V/μs	RL ≥ 2 kΩ	3
Closed-Loop Bandwidth	BW	0.4	0.6		MHz	AVCL = 1	3
Power Consumption	PD		50	60	mW	VS = ±15 V, no load	3
Power Consumption (low supply)	PD		3.5	4.5	mW	VS = ±3 V, no load	3
Supply Current	ISY		1.6	2	mA	VS = ±15 V, no load	3
Input Voltage Range	IVR	-13	14	13	V	VS = ±15 V, TA = 25°C (table 1 header)	3
Offset Adjustment Range		-3		3	mV	RP = 20 kΩ	3
Input Offset Voltage (−40°C to +85°C)	VOS		20	100	μV	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Average Input Offset Voltage Drift	TCVOS		0.7	1.2	μV/°C	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Input Offset Current (−40°C to +85°C)	IOS		0.5	4.5	nA	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Average Input Offset Current Drift	TCIOS		1.5	85	pA/°C	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Input Bias Current (−40°C to +85°C)	IB	-6	2.4	6	nA	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Average Input Bias Current Drift	TCIB		15	60	pA/°C	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Input Voltage Range (−40°C to +85°C)	IVR	-13	13.5	13	V	VS = ±15 V, −40°C ≤ TA ≤ +85°C (table 2 header)	4
Common-Mode Rejection Ratio (−40°C to +85°C)	CMRR	110	140		dB	VCM = ±13 V	4
Power Supply Rejection Ratio (−40°C to +85°C)	PSRR	106	115		dB	VS = ±3 V to ±18 V	4
Large-Signal Voltage Gain (−40°C to +85°C)	AVO	1000	4000		V/mV	RL ≥ 2 kΩ, VO = ±10 V	4
Output Voltage Swing (−40°C to +85°C)	VO	-12	13	12	V	RL ≥ 2 kΩ	4
Power Consumption (−40°C to +85°C)	PD		60	75	mW	VS = ±15 V, no load	4
Supply Current (−40°C to +85°C)	ISY		2	2.5	mA	VS = ±15 V, no load	4
Supply Voltage		-22		22	V		5
Internal Power Dissipation				500	mW		5
Differential Input Voltage		-30		30	V		5
Input Voltage		-22		22	V	For supplies less than ±22 V, equal to the supply voltage	5
Storage Temperature Range		-65		125	°C		5
Operating Temperature Range		-40		85	°C		5
Lead Temperature (Soldering)				300	°C	Soldering, 60 sec	5
DICE Junction Temperature	TJ	-65		150	°C	DICE	5
Thermal Resistance, Junction-to-Ambient (8-Lead SOIC)	θJA		158		°C/W	Device soldered to printed circuit board for SOIC package	5
Thermal Resistance, Junction-to-Case (8-Lead SOIC)	θJC		43		°C/W		5

CAD (KiCad official)

Symbol: OP177GSZ-REEL
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: op177gsz-reel-etched.step / op177gsz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); op177gsz-reel.step / op177gsz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (16 pp, sha256 5a5ff145b727a9a8, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF