component
ONET1151PRGTR
Public Made by Adomby adom
Texas Instruments Special Purpose Amplifiers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ONET1151PRGTR
Texas Instruments · Special Purpose Amplifiers · VQFN-16-EP(3x3)
ONET1151PRGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Circuit ground. |
| 2 | DIN+ | input | Non-inverted data input, differentially 100 Ω terminated to DIN-. |
| 3 | DIN- | input | Inverted data input, differentially 100 Ω terminated to DIN+. |
| 4 | GND | power_in | Circuit ground. |
| 5 | COC1 | passive | Offset cancellation filter capacitor plus terminal; connect an external capacitor to COC2 to lower the low frequency cutoff, or tie COC1 to COC2 to disable the offset cancellation loop. |
| 6 | COC2 | passive | Offset cancellation filter capacitor minus terminal; connect an external capacitor to COC1 to lower the low frequency cutoff, or tie COC1 to COC2 to disable the offset cancellation loop. |
| 7 | DIS | input | Disables the output stage when set to a high level. |
| 8 | LOS | output | Open-drain MOS loss-of-signal output, high indicates input amplitude is below the programmed threshold; requires an external 10 kΩ pull-up resistor to VCC. |
| 9 | VCC | power_in | 3.3-V supply voltage. |
| 10 | DOUT- | output | Inverted CML data output, on-chip 50 Ω back-terminated to VCC. |
| 11 | DOUT+ | output | Non-inverted CML data output, on-chip 50 Ω back-terminated to VCC. |
| 12 | VCC | power_in | 3.3-V supply voltage. |
| 13 | NC | unconnected | No connect, do not connect. |
| 14 | NC | unconnected | No connect, do not connect. |
| 15 | SCK | input | Serial interface clock input; connect a pull-up resistor (10 kΩ typical) to VCC. |
| 16 | SDA | bidirectional | Serial interface data pin; connect a pull-up resistor (10 kΩ typical) to VCC. |
| 17 | GND | power_in | Exposed die pad (EP) must be grounded and soldered to the board. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Amplifiers |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | 4 | V | 4 | ||
| Voltage at DIN+, DIN- | VDIN+, VDIN- | 0.5 | 4 | V | 4 | ||
| Voltage at LOS, COC1, COC2, DOUT+, DOUT-, DIS, SDA, SCK | VLOS etc. | -0.3 | 4 | V | 4 | ||
| Differential voltage between DIN+ and DIN- | VDIN,DIFF | -2.5 | 2.5 | V | 4 | ||
| Continuous current at inputs and outputs | IDIN+, IDIN-, IDOUT+, IDOUT- | 25 | mA | 4 | |||
| ESD rating at all pins | ESD | 2 | kV | HBM | 4 | ||
| Characterized free-air operating temperature range | TA | -40 | 100 | °C | 4 | ||
| Maximum junction temperature | TJ, max | 125 | °C | 4 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 4 | ||
| Case temperature | TC | -40 | 110 | °C | 4 | ||
| Lead temperature | TLEAD | 260 | °C | 1.6mm (1/16 inch) from case for 10 seconds | 4 | ||
| Supply voltage | VCC | 2.9 | 3.3 | 3.63 | V | TA = -40°C to +100°C | 4 |
| Supply voltage | VCC | 2.85 | 3.3 | 3.63 | V | TA = -30°C to +100°C | 4 |
| Operating free-air temperature | TA | -40 | 100 | °C | 4 | ||
| Digital input high voltage | VIH | 2 | V | 4 | |||
| Digital input low voltage | VIL | 0.8 | V | 4 | |||
| Supply current | IVCC | 40 | 52 | mA | DIS = 0, CML currents included | 4 | |
| Data input resistance | RIN | 100 | Ω | Differential | 4 | ||
| Data output resistance | ROUT | 50 | Ω | Single-ended, referenced to VCC | 4 | ||
| LOS HIGH voltage | 2.3 | V | ISOURCE = 50 µA with 10 kΩ pull-up to VCC | 4 | |||
| LOS LOW voltage | 0.4 | V | ISINK = 10 mA with 10 kΩ pull-up to VCC | 4 | |||
| -3dB bandwidth | f3dB-H | 7.5 | 9.5 | GHz | default settings | 5 | |
| Low frequency -3dB bandwidth | f3dB-L | 10 | 45 | kHz | With 330 pF COC capacitor | 5 | |
| Data input sensitivity | VIN,MIN | 6 | 9 | mVp-p | PRBS31 pattern at 11.3 Gbps, BER < 10-12 | 5 | |
| Data input sensitivity (output limited) | VIN,MIN | 20 | 40 | mVp-p | VOD-min ≥ 0.95 * VOD (output limited) | 5 | |
| Differential input return gain | SDD11 | -15 | dB | 0.01 GHz < f < 5 GHz | 5 | ||
| Differential input return gain | SDD11 | -8 | dB | 5 GHz < f < 12.1 GHz | 5 | ||
| Differential output return gain | SDD22 | -15 | dB | 0.01 GHz < f < 5 GHz | 5 | ||
| Differential output return gain | SDD22 | -8 | dB | 5 GHz < f < 12.1 GHz | 5 | ||
| Differential to common mode conversion gain | SCD11 | -15 | dB | 0.01 GHz < f < 12.1 GHz | 5 | ||
| Common mode output return gain | SCC22 | -13 | dB | 0.01 GHz < f < 5 GHz | 5 | ||
| Common mode output return gain | SCC22 | -9 | dB | 5 GHz < f < 12.1 GHz | 5 | ||
| Small signal gain | A | 26 | 33 | dB | 5 | ||
| Data input overload | VIN-MAX | 2000 | mVp-p | BIAS (Reg7 bit 0) set to 1 | 5 | ||
| Deterministic jitter | DJ | 3 | 8 | psp-p | VIN = 15 mVp-p, K28.5 pattern, 11.3 Gbps | 5 | |
| Deterministic jitter | DJ | 3 | 10 | psp-p | VIN = 30 mVp-p, K28.5 pattern, 11.3 Gbps | 5 | |
| Deterministic jitter | DJ | 6 | 15 | psp-p | VIN = 2000 mVp-p, K28.5 pattern, 11.3 Gbps | 5 | |
| Random jitter | RJ | 1 | psrms | VIN = 30 mVp-p | 5 | ||
| Differential data output voltage | VOD | 380 | mVp-p | VIN > 30 mVp-p, DIS = 0, AMP[0..2] = 000 | 5 | ||
| Differential data output voltage | VOD | 820 | mVp-p | VIN > 30 mVp-p, DIS = 0, AMP[0..2] = 111 | 5 | ||
| Differential output voltage, disabled | VOD | 5 | mVrms | DIS = 1 | 5 | ||
| Output de-emphasis step size | VPREEM | 1 | dB | 5 | |||
| Output rise time | tR | 30 | 40 | ps | 20%, 80%, VIN > 30 mVp-p | 5 | |
| Output fall time | tF | 30 | 40 | ps | 20%, 80%, VIN > 30 mVp-p | 5 | |
| AC common mode output voltage | CMOV | 7 | mVrms | PRBS31 pattern; AMP[0..2] = 010 | 5 | ||
| LOW LOS assert threshold range min. | VTH | 15 | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 0 | 5 | ||
| LOW LOS assert threshold range max. | VTH | 35 | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 0 | 5 | ||
| HIGH LOS assert threshold range min. | VTH | 35 | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 1 | 5 | ||
| HIGH LOS assert threshold range max. | VTH | 80 | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 1 | 5 | ||
| LOS hysteresis (electrical) | 2 | 4 | 6.5 | dB | K28.5 pattern at 11.3 Gbps | 5 | |
| LOS assert time | TLOS_AST | 2.5 | 10 | 80 | µs | 5 | |
| LOS deassert time | TLOS_DEA | 2.5 | 10 | 80 | µs | 5 | |
| Disable response time | TDIS | 20 | ns | 5 | |||
| SCK clock frequency | fSCK | 400 | kHz | 8 | |||
| Bus free time between STOP and START | tBUF | 1.3 | μs | 8 | |||
| Low period of SCK clock | tLOW | 1.3 | μs | 8 | |||
| High period of SCK clock | tHIGH | 0.6 | μs | 8 | |||
| Data setup time | tSUDAT | 100 | ns | 8 | |||
| Rise time of SDA and SCK | tR | 300 | ns | 8 | |||
| Fall time of SDA and SCK | tF | 300 | ns | 8 |
CAD (KiCad official)
- Symbol:
ONET1151PRGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
onet1151prgtr-etched.step/onet1151prgtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);onet1151prgtr.step/onet1151prgtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
52e306f1d3fd0f9f, retrieved 2026-10-31, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ONET1151PRGTR
**Texas Instruments** · Special Purpose Amplifiers · VQFN-16-EP(3x3)
ONET1151PRGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Circuit ground. |
| 2 | DIN+ | input | Non-inverted data input, differentially 100 Ω terminated to DIN-. |
| 3 | DIN- | input | Inverted data input, differentially 100 Ω terminated to DIN+. |
| 4 | GND | power_in | Circuit ground. |
| 5 | COC1 | passive | Offset cancellation filter capacitor plus terminal; connect an external capacitor to COC2 to lower the low frequency cutoff, or tie COC1 to COC2 to disable the offset cancellation loop. |
| 6 | COC2 | passive | Offset cancellation filter capacitor minus terminal; connect an external capacitor to COC1 to lower the low frequency cutoff, or tie COC1 to COC2 to disable the offset cancellation loop. |
| 7 | DIS | input | Disables the output stage when set to a high level. |
| 8 | LOS | output | Open-drain MOS loss-of-signal output, high indicates input amplitude is below the programmed threshold; requires an external 10 kΩ pull-up resistor to VCC. |
| 9 | VCC | power_in | 3.3-V supply voltage. |
| 10 | DOUT- | output | Inverted CML data output, on-chip 50 Ω back-terminated to VCC. |
| 11 | DOUT+ | output | Non-inverted CML data output, on-chip 50 Ω back-terminated to VCC. |
| 12 | VCC | power_in | 3.3-V supply voltage. |
| 13 | NC | unconnected | No connect, do not connect. |
| 14 | NC | unconnected | No connect, do not connect. |
| 15 | SCK | input | Serial interface clock input; connect a pull-up resistor (10 kΩ typical) to VCC. |
| 16 | SDA | bidirectional | Serial interface data pin; connect a pull-up resistor (10 kΩ typical) to VCC. |
| 17 | GND | power_in | Exposed die pad (EP) must be grounded and soldered to the board. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Amplifiers |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | | 4 | V | | 4 |
| Voltage at DIN+, DIN- | VDIN+, VDIN- | 0.5 | | 4 | V | | 4 |
| Voltage at LOS, COC1, COC2, DOUT+, DOUT-, DIS, SDA, SCK | VLOS etc. | -0.3 | | 4 | V | | 4 |
| Differential voltage between DIN+ and DIN- | VDIN,DIFF | -2.5 | | 2.5 | V | | 4 |
| Continuous current at inputs and outputs | IDIN+, IDIN-, IDOUT+, IDOUT- | | | 25 | mA | | 4 |
| ESD rating at all pins | ESD | | | 2 | kV | HBM | 4 |
| Characterized free-air operating temperature range | TA | -40 | | 100 | °C | | 4 |
| Maximum junction temperature | TJ, max | | | 125 | °C | | 4 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 4 |
| Case temperature | TC | -40 | | 110 | °C | | 4 |
| Lead temperature | TLEAD | | | 260 | °C | 1.6mm (1/16 inch) from case for 10 seconds | 4 |
| Supply voltage | VCC | 2.9 | 3.3 | 3.63 | V | TA = -40°C to +100°C | 4 |
| Supply voltage | VCC | 2.85 | 3.3 | 3.63 | V | TA = -30°C to +100°C | 4 |
| Operating free-air temperature | TA | -40 | | 100 | °C | | 4 |
| Digital input high voltage | VIH | 2 | | | V | | 4 |
| Digital input low voltage | VIL | | | 0.8 | V | | 4 |
| Supply current | IVCC | | 40 | 52 | mA | DIS = 0, CML currents included | 4 |
| Data input resistance | RIN | | 100 | | Ω | Differential | 4 |
| Data output resistance | ROUT | | 50 | | Ω | Single-ended, referenced to VCC | 4 |
| LOS HIGH voltage | | 2.3 | | | V | ISOURCE = 50 µA with 10 kΩ pull-up to VCC | 4 |
| LOS LOW voltage | | | | 0.4 | V | ISINK = 10 mA with 10 kΩ pull-up to VCC | 4 |
| -3dB bandwidth | f3dB-H | 7.5 | 9.5 | | GHz | default settings | 5 |
| Low frequency -3dB bandwidth | f3dB-L | | 10 | 45 | kHz | With 330 pF COC capacitor | 5 |
| Data input sensitivity | VIN,MIN | | 6 | 9 | mVp-p | PRBS31 pattern at 11.3 Gbps, BER < 10-12 | 5 |
| Data input sensitivity (output limited) | VIN,MIN | | 20 | 40 | mVp-p | VOD-min ≥ 0.95 * VOD (output limited) | 5 |
| Differential input return gain | SDD11 | | | -15 | dB | 0.01 GHz < f < 5 GHz | 5 |
| Differential input return gain | SDD11 | | | -8 | dB | 5 GHz < f < 12.1 GHz | 5 |
| Differential output return gain | SDD22 | | | -15 | dB | 0.01 GHz < f < 5 GHz | 5 |
| Differential output return gain | SDD22 | | | -8 | dB | 5 GHz < f < 12.1 GHz | 5 |
| Differential to common mode conversion gain | SCD11 | | | -15 | dB | 0.01 GHz < f < 12.1 GHz | 5 |
| Common mode output return gain | SCC22 | | | -13 | dB | 0.01 GHz < f < 5 GHz | 5 |
| Common mode output return gain | SCC22 | | | -9 | dB | 5 GHz < f < 12.1 GHz | 5 |
| Small signal gain | A | 26 | 33 | | dB | | 5 |
| Data input overload | VIN-MAX | 2000 | | | mVp-p | BIAS (Reg7 bit 0) set to 1 | 5 |
| Deterministic jitter | DJ | | 3 | 8 | psp-p | VIN = 15 mVp-p, K28.5 pattern, 11.3 Gbps | 5 |
| Deterministic jitter | DJ | | 3 | 10 | psp-p | VIN = 30 mVp-p, K28.5 pattern, 11.3 Gbps | 5 |
| Deterministic jitter | DJ | | 6 | 15 | psp-p | VIN = 2000 mVp-p, K28.5 pattern, 11.3 Gbps | 5 |
| Random jitter | RJ | | 1 | | psrms | VIN = 30 mVp-p | 5 |
| Differential data output voltage | VOD | | 380 | | mVp-p | VIN > 30 mVp-p, DIS = 0, AMP[0..2] = 000 | 5 |
| Differential data output voltage | VOD | | 820 | | mVp-p | VIN > 30 mVp-p, DIS = 0, AMP[0..2] = 111 | 5 |
| Differential output voltage, disabled | VOD | | | 5 | mVrms | DIS = 1 | 5 |
| Output de-emphasis step size | VPREEM | | 1 | | dB | | 5 |
| Output rise time | tR | | 30 | 40 | ps | 20%, 80%, VIN > 30 mVp-p | 5 |
| Output fall time | tF | | 30 | 40 | ps | 20%, 80%, VIN > 30 mVp-p | 5 |
| AC common mode output voltage | CMOV | | 7 | | mVrms | PRBS31 pattern; AMP[0..2] = 010 | 5 |
| LOW LOS assert threshold range min. | VTH | | 15 | | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 0 | 5 |
| LOW LOS assert threshold range max. | VTH | | 35 | | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 0 | 5 |
| HIGH LOS assert threshold range min. | VTH | | 35 | | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 1 | 5 |
| HIGH LOS assert threshold range max. | VTH | | 80 | | mVp-p | K28.5 pattern at 11.3 Gbps, LOSRNG = 1 | 5 |
| LOS hysteresis (electrical) | | 2 | 4 | 6.5 | dB | K28.5 pattern at 11.3 Gbps | 5 |
| LOS assert time | TLOS_AST | 2.5 | 10 | 80 | µs | | 5 |
| LOS deassert time | TLOS_DEA | 2.5 | 10 | 80 | µs | | 5 |
| Disable response time | TDIS | | | 20 | ns | | 5 |
| SCK clock frequency | fSCK | | | 400 | kHz | | 8 |
| Bus free time between STOP and START | tBUF | 1.3 | | | μs | | 8 |
| Low period of SCK clock | tLOW | 1.3 | | | μs | | 8 |
| High period of SCK clock | tHIGH | 0.6 | | | μs | | 8 |
| Data setup time | tSUDAT | 100 | | | ns | | 8 |
| Rise time of SDA and SCK | tR | | | 300 | ns | | 8 |
| Fall time of SDA and SCK | tF | | | 300 | ns | | 8 |
## CAD (KiCad official)
- Symbol: `ONET1151PRGTR`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `onet1151prgtr-etched.step` / `onet1151prgtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `onet1151prgtr.step` / `onet1151prgtr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/onet1151p.pdf) (25 pp, sha256 `52e306f1d3fd0f9f`, retrieved 2026-10-31, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/onet1151prgtr-datasheet.pdf)