# O919A14ETRGZRQ1

**Texas Instruments** · Power Management - Specialized · VQFN-48-EP(7x7)

O919A14ETRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO_4 | bidirectional | General-purpose I/O in the VIO domain with secondary functions REGEN2 output and I2C2_SCL_SCE (DVS I2C clock / SPI chip enable); software-programmable pullup/pulldown, float if unused. |
| 2 | GPIO_2 | bidirectional | General-purpose I/O in the VIO domain with secondary functions ENABLE1 input and I2C2_SDA_SDO (DVS I2C data / SPI output data); software-programmable pullup/pulldown, float if unused. |
| 3 | LDO5_IN | power_in | Power input voltage for the LDO5 regulator, connect to system supply. |
| 4 | LDO5_OUT | power_out | LDO5 output voltage, left floating if unused. |
| 5 | LDO_IN | power_in | Power input voltage for LDO regulator, connect to system supply. |
| 6 | NC | unconnected | No connection, leave floating. |
| 7 | LDO4_OUT | power_out | LDO4 output voltage, left floating if unused. |
| 8 | LDO4_IN | power_in | Power input voltage for the LDO4 regulator, connect to system supply. |
| 9 | SMPS3_FDBK | input | Output voltage-sense (feedback) input for SMPS3, connect to ground if unused. |
| 10 | SMPS3_IN | power_in | Power input for SMPS3, connect to system supply. |
| 11 | SMPS3_SW | power_out | Switch node of SMPS3; connect output inductor, float if unused. |
| 12 | GPIO_0 | bidirectional | General-purpose I/O at VRTC level (5.25-V fail-safe tolerant) with secondary functions ENABLE2, PWRDOWN input and REGEN1 output; ground or VRTC if unused. |
| 13 | GPIO_1 | bidirectional | General-purpose I/O at VRTC level (5.25-V fail-safe tolerant) with secondary functions RESET_IN, VBUS_SENSE and NRESWARM inputs; float if unused. |
| 14 | GPIO_3 | bidirectional | General-purpose I/O at VRTC level (5.25-V fail-safe tolerant) with secondary functions REGEN1 output, ENABLE2 input and SYNCDCDC external SMPS clock sync input; float if unused. |
| 15 | GPIO_5 | bidirectional | General-purpose I/O at VRTC level (5.25-V fail-safe tolerant) with secondary functions POWERHOLD input and REGEN3 output; ground if unused. |
| 16 | BOOT | input | Tri-level boot input for power-up sequence selection, connect to ground or VRTC. |
| 17 | SMPS4_FDBK | input | Output voltage-sense (feedback) input for SMPS4, connect to ground if unused. |
| 18 | SMPS4_IN | power_in | Power input for SMPS4, connect to system supply. |
| 19 | SMPS4_SW | power_out | Switch node of SMPS4; connect output inductor, float if unused. |
| 20 | VPROG | bidirectional | OTP programming voltage input (absolute max 7 V) with secondary function TESTV output; ground or float if unused. |
| 21 | LDO2_OUT | power_out | LDO2 output voltage, left floating if unused. |
| 22 | LDO12_IN | power_in | Power input voltage for LDO1 and LDO2 regulators, connect to system supply. |
| 23 | LDO1_OUT | power_out | LDO1 output voltage, left floating if unused. |
| 24 | PWRON | input | External power-on event (on-button switch-on) input with fixed pullup, active low at VSYS (VCCA) level. |
| 25 | RESET_OUT | output | System reset or power-on output at VIO level (low = reset, high = active or sleep), push-pull or open-drain. |
| 26 | INT | output | Maskable interrupt output request to the host processor at VIO level, active low by default. |
| 27 | GPIO_6 | bidirectional | General-purpose I/O at VRTC level with secondary functions NSLEEP input, POWERGOOD output and REGEN3 output; ground if unused. |
| 28 | SMPS2_FDBK | input | Output voltage-sense input for SMPS2 or differential negative sense input for SMPS12 in dual-phase configuration, connect to ground if unused. |
| 29 | SMPS2_IN | power_in | Power input for SMPS2, connect to system supply. |
| 30 | SMPS2_SW | power_out | Switch node of SMPS2; connect output inductor, float if unused. |
| 31 | SMPS1_SW | power_out | Switch node of SMPS1; connect output inductor, float if unused. |
| 32 | SMPS1_IN | power_in | Power input for SMPS1, connect to system supply. |
| 33 | SMPS1_FDBK | input | Output voltage-sense input for SMPS1 or differential positive sense input for SMPS12 in dual-phase configuration, connect to ground if unused. |
| 34 | VIO_IN | power_in | Digital supply input for GPIOs and I/O supply voltage (1.8 V: 1.71 to 1.89 V; 3.3 V: 3.135 to 3.465 V). |
| 35 | I2C1_SCL_SCK | input | Control I2C serial clock (external pullup) and SPI clock signal at VIO level. |
| 36 | I2C1_SDA_SDI | bidirectional | Control I2C serial bidirectional data (external pullup) and SPI input data signal at VIO level. |
| 37 | VCC_SENSE | input | System supply sense line, 3.135 V to VCCA recommended (VCCA - 1 V when HIGH_VCC_SENSE = 1). |
| 38 | ADCIN1 | input | GPADC input 1 (absolute max 2.4 V), connect to ground if unused. |
| 39 | ADCIN2 | input | GPADC input 2 (absolute max 2.4 V), connect to ground if unused. |
| 40 | VBG | output | Bandgap reference voltage output. |
| 41 | REFGND | power_in | System reference ground, connect to ground. |
| 42 | VCCA | power_in | Analog input voltage for internal LDOs, system supply 3.135 V to 5.25 V (3.8 V nominal). |
| 43 | LDOVANA_OUT | power_out | Internal LDOVANA output voltage. |
| 44 | LDOVRTC_OUT | power_out | Internal LDOVRTC output voltage; a pulldown resistor (minimum 3.9 kΩ) is recommended to support rapid power off and on. |
| 45 | NC | unconnected | No connection, leave floating. |
| 46 | SMPS_IN | power_in | Power input for SMPS, connect to system supply. |
| 47 | NC | unconnected | No connection, leave floating. |
| 48 | SYNCCLKOUT | output | Primary function 2.2-MHz fallback SMPS switching frequency; secondary function 32-kHz digital-gated output clock when VIO_IN is present. |
| 49 | PGND | power_in | Thermal pad (PGND), connect to ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management (PMIC) |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `O919A14ETRGZRQ1`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `o919a14etrgzrq1-etched.step` / `o919a14etrgzrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `o919a14etrgzrq1.step` / `o919a14etrgzrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65919-q1) (91 pp, sha256 `620c3bdc2d08acc8`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/o919a14etrgzrq1-datasheet.pdf)