component
O919A14CTRGZRQ1
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+86@@ -0,0 +1,86 @@+# O919A14CTRGZRQ1++**Texas Instruments** · Power Management - Specialized · VQFN-48-EP(7x7)++O919A14CTRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO_4 | bidirectional | General-purpose I/O in the VIO domain, with secondary functions REGEN2 (external regulator enable output 2) and I2C2_SCL_SCE (DVS I2C clock or SPI chip enable). |+| 2 | GPIO_2 | bidirectional | General-purpose I/O in the VIO domain, with secondary functions ENABLE1 (peripheral power request input 1) and I2C2_SDA_SDO (DVS I2C data or SPI output data). |+| 3 | LDO5_IN | power_in | Power input voltage for the LDO5 regulator, connected to the system supply. |+| 4 | LDO5_OUT | power_out | LDO5 output voltage; leave floating if not used. |+| 5 | LDO_IN | power_in | Power input voltage for the LDO regulator, connected to the system supply. |+| 6 | NC | unconnected | No connection; leave floating. |+| 7 | LDO4_OUT | power_out | LDO4 output voltage; leave floating if not used. |+| 8 | LDO4_IN | power_in | Power input voltage for the LDO4 regulator, connected to the system supply. |+| 9 | SMPS3_FDBK | input | Output voltage-sense (feedback) input for SMPS3; connect to ground if not used. |+| 10 | SMPS3_IN | power_in | Power input for SMPS3, connected to the system supply. |+| 11 | SMPS3_SW | output | Switch node of SMPS3; connect the output inductor. |+| 12 | GPIO_0 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions ENABLE2, PWRDOWN and REGEN1. |+| 13 | GPIO_1 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions RESET_IN, VBUS_SENSE and NRESWARM. |+| 14 | GPIO_3 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions REGEN1, ENABLE2 and SYNCDCDC (SMPS clock sync input). |+| 15 | GPIO_5 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions POWERHOLD input and REGEN3 output. |+| 16 | BOOT | input | Tri-level boot input for power-up sequence selection; connect to ground or VRTC if not used. |+| 17 | SMPS4_FDBK | input | Output voltage-sense (feedback) input for SMPS4; connect to ground if not used. |+| 18 | SMPS4_IN | power_in | Power input for SMPS4, connected to the system supply. |+| 19 | SMPS4_SW | output | Switch node of SMPS4; connect the output inductor. |+| 20 | VPROG | input | OTP programming voltage input (absolute maximum 7 V), with secondary function TESTV output; connect to ground or leave floating if not used. |+| 21 | LDO2_OUT | power_out | LDO2 output voltage; leave floating if not used. |+| 22 | LDO12_IN | power_in | Power input voltage for the LDO1 and LDO2 regulators, connected to the system supply. |+| 23 | LDO1_OUT | power_out | LDO1 output voltage; leave floating if not used. |+| 24 | PWRON | input | External power-on event (on-button switch-on) input with fixed pullup, active low in the VSYS (VCCA) domain. |+| 25 | RESET_OUT | output | System reset or power-on output in the VIO domain (low = reset, high = active or sleep). |+| 26 | INT | output | Maskable interrupt output request to the host processor, in the VIO domain, active low by default. |+| 27 | GPIO_6 | bidirectional | General-purpose I/O in the VRTC domain, with secondary functions NSLEEP, POWERGOOD and REGEN3. |+| 28 | SMPS2_FDBK | input | Output voltage-sense input for SMPS2, or differential negative sense input for SMPS12 in dual-phase configuration; connect to ground if not used. |+| 29 | SMPS2_IN | power_in | Power input for SMPS2, connected to the system supply. |+| 30 | SMPS2_SW | output | Switch node of SMPS2; connect the output inductor. |+| 31 | SMPS1_SW | output | Switch node of SMPS1; connect the output inductor. |+| 32 | SMPS1_IN | power_in | Power input for SMPS1, connected to the system supply. |+| 33 | SMPS1_FDBK | input | Output voltage-sense input for SMPS1, or differential positive sense input for SMPS12 in dual-phase configuration; connect to ground if not used. |+| 34 | VIO_IN | power_in | Digital supply input for GPIOs and I/O supply voltage, 1.8 V (1.71 to 1.89 V) or 3.3 V (3.135 to 3.465 V). |+| 35 | I2C1_SCL_SCK | input | Control I2C serial clock (external pullup) and SPI clock signal, in the VIO domain. |+| 36 | I2C1_SDA_SDI | bidirectional | Control I2C serial bidirectional data (external pullup, open-drain) and SPI input data signal, in the VIO domain. |+| 37 | VCC_SENSE | input | System supply sense line, 3.135 V to VCCA recommended (absolute maximum 7 V). |+| 38 | ADCIN1 | input | GPADC input 1 (absolute maximum 2.4 V); connect to ground if not used. |+| 39 | ADCIN2 | input | GPADC input 2 (absolute maximum 2.4 V); connect to ground if not used. |+| 40 | VBG | output | Bandgap reference voltage output. |+| 41 | REFGND | power_in | System reference ground; connect to ground. |+| 42 | VCCA | power_in | Analog input voltage for internal LDOs and system supply, 3.135 V to 5.25 V recommended (named VSYS). |+| 43 | LDOVANA_OUT | power_out | Internal LDOVANA output voltage. |+| 44 | LDOVRTC_OUT | power_out | Internal LDOVRTC output voltage; connect a pulldown resistor to support rapid power off and on. |+| 45 | NC | unconnected | No connection; leave floating. |+| 46 | SMPS_IN | power_in | Power input for SMPS, connected to the system supply. |+| 47 | NC | unconnected | No connection; leave floating. |+| 48 | SYNCCLKOUT | output | 2.2-MHz fallback switching frequency output for the SMPS, with secondary function 32-kHz digital-gated output clock when VIO_IN is present. |+| 49 | PGND | power_in | Thermal pad (PGND) on the bottom of the package, connected to ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Power Management (PMIC) |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `O919A14CTRGZRQ1`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `o919a14ctrgzrq1-etched.step` / `o919a14ctrgzrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `o919a14ctrgzrq1.step` / `o919a14ctrgzrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65919-q1) (91 pp, sha256 `620c3bdc2d08acc8`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/o919a14ctrgzrq1-datasheet.pdf)
page.jsonadded+447@@ -0,0 +1,447 @@+{+ "slug": "o919a14ctrgzrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Power Management - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "o919a14ctrgzrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "o919a14ctrgzrq1.kicad_sym",+ "o919a14ctrgzrq1.kicad_mod",+ "o919a14ctrgzrq1.glb",+ "o919a14ctrgzrq1.step",+ "o919a14ctrgzrq1.lbr",+ "docs/hero.png",+ "docs/o919a14ctrgzrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "o919a14ctrgzrq1-hero.glb",+ "o919a14ctrgzrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "O919A14CTRGZRQ1",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps65919-q1",+ "parts": {+ "symbol": "o919a14ctrgzrq1.kicad_sym",+ "footprint": "o919a14ctrgzrq1.kicad_mod",+ "model_3d": "o919a14ctrgzrq1-hero.glb",+ "model_3d_plain": "o919a14ctrgzrq1.glb",+ "model_3d_step": "o919a14ctrgzrq1-etched.step",+ "model_3d_step_plain": "o919a14ctrgzrq1.step",+ "lbr": "o919a14ctrgzrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2864918",+ "digikey": "296-51480-2-ND",+ "mouser": "595-O919A14CTRGZRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:40:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-51480-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-O919A14CTRGZRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO_4",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VIO domain, with secondary functions REGEN2 (external regulator enable output 2) and I2C2_SCL_SCE (DVS I2C clock or SPI chip enable)."+ },+ {+ "number": "2",+ "name": "GPIO_2",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VIO domain, with secondary functions ENABLE1 (peripheral power request input 1) and I2C2_SDA_SDO (DVS I2C data or SPI output data)."+ },+ {+ "number": "3",+ "name": "LDO5_IN",+ "type": "power_in",+ "description": "Power input voltage for the LDO5 regulator, connected to the system supply."+ },+ {+ "number": "4",+ "name": "LDO5_OUT",+ "type": "power_out",+ "description": "LDO5 output voltage; leave floating if not used."+ },+ {+ "number": "5",+ "name": "LDO_IN",+ "type": "power_in",+ "description": "Power input voltage for the LDO regulator, connected to the system supply."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave floating."+ },+ {+ "number": "7",+ "name": "LDO4_OUT",+ "type": "power_out",+ "description": "LDO4 output voltage; leave floating if not used."+ },+ {+ "number": "8",+ "name": "LDO4_IN",+ "type": "power_in",+ "description": "Power input voltage for the LDO4 regulator, connected to the system supply."+ },+ {+ "number": "9",+ "name": "SMPS3_FDBK",+ "type": "input",+ "description": "Output voltage-sense (feedback) input for SMPS3; connect to ground if not used."+ },+ {+ "number": "10",+ "name": "SMPS3_IN",+ "type": "power_in",+ "description": "Power input for SMPS3, connected to the system supply."+ },+ {+ "number": "11",+ "name": "SMPS3_SW",+ "type": "output",+ "description": "Switch node of SMPS3; connect the output inductor."+ },+ {+ "number": "12",+ "name": "GPIO_0",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions ENABLE2, PWRDOWN and REGEN1."+ },+ {+ "number": "13",+ "name": "GPIO_1",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions RESET_IN, VBUS_SENSE and NRESWARM."+ },+ {+ "number": "14",+ "name": "GPIO_3",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions REGEN1, ENABLE2 and SYNCDCDC (SMPS clock sync input)."+ },+ {+ "number": "15",+ "name": "GPIO_5",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions POWERHOLD input and REGEN3 output."+ },+ {+ "number": "16",+ "name": "BOOT",+ "type": "input",+ "description": "Tri-level boot input for power-up sequence selection; connect to ground or VRTC if not used."+ },+ {+ "number": "17",+ "name": "SMPS4_FDBK",+ "type": "input",+ "description": "Output voltage-sense (feedback) input for SMPS4; connect to ground if not used."+ },+ {+ "number": "18",+ "name": "SMPS4_IN",+ "type": "power_in",+ "description": "Power input for SMPS4, connected to the system supply."+ },+ {+ "number": "19",+ "name": "SMPS4_SW",+ "type": "output",+ "description": "Switch node of SMPS4; connect the output inductor."+ },+ {+ "number": "20",+ "name": "VPROG",+ "type": "input",+ "description": "OTP programming voltage input (absolute maximum 7 V), with secondary function TESTV output; connect to ground or leave floating if not used."+ },+ {+ "number": "21",+ "name": "LDO2_OUT",+ "type": "power_out",+ "description": "LDO2 output voltage; leave floating if not used."+ },+ {+ "number": "22",+ "name": "LDO12_IN",+ "type": "power_in",+ "description": "Power input voltage for the LDO1 and LDO2 regulators, connected to the system supply."+ },+ {+ "number": "23",+ "name": "LDO1_OUT",+ "type": "power_out",+ "description": "LDO1 output voltage; leave floating if not used."+ },+ {+ "number": "24",+ "name": "PWRON",+ "type": "input",+ "description": "External power-on event (on-button switch-on) input with fixed pullup, active low in the VSYS (VCCA) domain."+ },+ {+ "number": "25",+ "name": "RESET_OUT",+ "type": "output",+ "description": "System reset or power-on output in the VIO domain (low = reset, high = active or sleep)."+ },+ {+ "number": "26",+ "name": "INT",+ "type": "output",+ "description": "Maskable interrupt output request to the host processor, in the VIO domain, active low by default."+ },+ {+ "number": "27",+ "name": "GPIO_6",+ "type": "bidirectional",+ "description": "General-purpose I/O in the VRTC domain, with secondary functions NSLEEP, POWERGOOD and REGEN3."+ },+ {+ "number": "28",+ "name": "SMPS2_FDBK",+ "type": "input",+ "description": "Output voltage-sense input for SMPS2, or differential negative sense input for SMPS12 in dual-phase configuration; connect to ground if not used."+ },+ {+ "number": "29",+ "name": "SMPS2_IN",+ "type": "power_in",+ "description": "Power input for SMPS2, connected to the system supply."+ },+ {+ "number": "30",+ "name": "SMPS2_SW",+ "type": "output",+ "description": "Switch node of SMPS2; connect the output inductor."+ },+ {+ "number": "31",+ "name": "SMPS1_SW",+ "type": "output",+ "description": "Switch node of SMPS1; connect the output inductor."+ },+ {+ "number": "32",+ "name": "SMPS1_IN",+ "type": "power_in",+ "description": "Power input for SMPS1, connected to the system supply."+ },+ {+ "number": "33",+ "name": "SMPS1_FDBK",+ "type": "input",+ "description": "Output voltage-sense input for SMPS1, or differential positive sense input for SMPS12 in dual-phase configuration; connect to ground if not used."+ },+ {+ "number": "34",+ "name": "VIO_IN",+ "type": "power_in",+ "description": "Digital supply input for GPIOs and I/O supply voltage, 1.8 V (1.71 to 1.89 V) or 3.3 V (3.135 to 3.465 V)."+ },+ {+ "number": "35",+ "name": "I2C1_SCL_SCK",+ "type": "input",+ "description": "Control I2C serial clock (external pullup) and SPI clock signal, in the VIO domain."+ },+ {+ "number": "36",+ "name": "I2C1_SDA_SDI",+ "type": "bidirectional",+ "description": "Control I2C serial bidirectional data (external pullup, open-drain) and SPI input data signal, in the VIO domain."+ },+ {+ "number": "37",+ "name": "VCC_SENSE",+ "type": "input",+ "description": "System supply sense line, 3.135 V to VCCA recommended (absolute maximum 7 V)."+ },+ {+ "number": "38",+ "name": "ADCIN1",+ "type": "input",+ "description": "GPADC input 1 (absolute maximum 2.4 V); connect to ground if not used."+ },+ {+ "number": "39",+ "name": "ADCIN2",+ "type": "input",+ "description": "GPADC input 2 (absolute maximum 2.4 V); connect to ground if not used."+ },+ {+ "number": "40",+ "name": "VBG",+ "type": "output",+ "description": "Bandgap reference voltage output."+ },+ {+ "number": "41",+ "name": "REFGND",+ "type": "power_in",+ "description": "System reference ground; connect to ground."+ },+ {+ "number": "42",+ "name": "VCCA",+ "type": "power_in",+ "description": "Analog input voltage for internal LDOs and system supply, 3.135 V to 5.25 V recommended (named VSYS)."+ },+ {+ "number": "43",+ "name": "LDOVANA_OUT",+ "type": "power_out",+ "description": "Internal LDOVANA output voltage."+ },+ {+ "number": "44",+ "name": "LDOVRTC_OUT",+ "type": "power_out",+ "description": "Internal LDOVRTC output voltage; connect a pulldown resistor to support rapid power off and on."+ },+ {+ "number": "45",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave floating."+ },+ {+ "number": "46",+ "name": "SMPS_IN",+ "type": "power_in",+ "description": "Power input for SMPS, connected to the system supply."+ },+ {+ "number": "47",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; leave floating."+ },+ {+ "number": "48",+ "name": "SYNCCLKOUT",+ "type": "output",+ "description": "2.2-MHz fallback switching frequency output for the SMPS, with secondary function 32-kHz digital-gated output clock when VIO_IN is present."+ },+ {+ "number": "49",+ "name": "PGND",+ "type": "power_in",+ "description": "Thermal pad (PGND) on the bottom of the package, connected to ground."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The thermal pad (labeled PGND in the Figure 3-1 pin drawing) has no pin number on the package, so it; The pin-to-number mapping was taken from the Pin Attributes table (Section 3.1), not from the Figure; Pin types for the GPIOs and I2C pins are bidirectional in KiCad terms, while open-drain or push-pull",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 34,+ "cost_usd": 0.214,+ "at": "2026-10-08T19:39:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps65919-q1",+ "pages": 91,+ "sha256": "620c3bdc2d08acc8",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "o919a14ctrgzrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "o919a14ctrgzrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "254fa1f8653136a7c3d80a723fcfd9d633f005df2c9c15682a2557b6917a7579",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}