component
O919A14CTRGZRQ1
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownO919A14CTRGZRQ1
Texas Instruments · Power Management - Specialized · VQFN-48-EP(7x7)
O919A14CTRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO_4 | bidirectional | General-purpose I/O in the VIO domain, with secondary functions REGEN2 (external regulator enable output 2) and I2C2_SCL_SCE (DVS I2C clock or SPI chip enable). |
| 2 | GPIO_2 | bidirectional | General-purpose I/O in the VIO domain, with secondary functions ENABLE1 (peripheral power request input 1) and I2C2_SDA_SDO (DVS I2C data or SPI output data). |
| 3 | LDO5_IN | power_in | Power input voltage for the LDO5 regulator, connected to the system supply. |
| 4 | LDO5_OUT | power_out | LDO5 output voltage; leave floating if not used. |
| 5 | LDO_IN | power_in | Power input voltage for the LDO regulator, connected to the system supply. |
| 6 | NC | unconnected | No connection; leave floating. |
| 7 | LDO4_OUT | power_out | LDO4 output voltage; leave floating if not used. |
| 8 | LDO4_IN | power_in | Power input voltage for the LDO4 regulator, connected to the system supply. |
| 9 | SMPS3_FDBK | input | Output voltage-sense (feedback) input for SMPS3; connect to ground if not used. |
| 10 | SMPS3_IN | power_in | Power input for SMPS3, connected to the system supply. |
| 11 | SMPS3_SW | output | Switch node of SMPS3; connect the output inductor. |
| 12 | GPIO_0 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions ENABLE2, PWRDOWN and REGEN1. |
| 13 | GPIO_1 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions RESET_IN, VBUS_SENSE and NRESWARM. |
| 14 | GPIO_3 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions REGEN1, ENABLE2 and SYNCDCDC (SMPS clock sync input). |
| 15 | GPIO_5 | bidirectional | General-purpose I/O in the VRTC domain (5.25-V fail-safe), with secondary functions POWERHOLD input and REGEN3 output. |
| 16 | BOOT | input | Tri-level boot input for power-up sequence selection; connect to ground or VRTC if not used. |
| 17 | SMPS4_FDBK | input | Output voltage-sense (feedback) input for SMPS4; connect to ground if not used. |
| 18 | SMPS4_IN | power_in | Power input for SMPS4, connected to the system supply. |
| 19 | SMPS4_SW | output | Switch node of SMPS4; connect the output inductor. |
| 20 | VPROG | input | OTP programming voltage input (absolute maximum 7 V), with secondary function TESTV output; connect to ground or leave floating if not used. |
| 21 | LDO2_OUT | power_out | LDO2 output voltage; leave floating if not used. |
| 22 | LDO12_IN | power_in | Power input voltage for the LDO1 and LDO2 regulators, connected to the system supply. |
| 23 | LDO1_OUT | power_out | LDO1 output voltage; leave floating if not used. |
| 24 | PWRON | input | External power-on event (on-button switch-on) input with fixed pullup, active low in the VSYS (VCCA) domain. |
| 25 | RESET_OUT | output | System reset or power-on output in the VIO domain (low = reset, high = active or sleep). |
| 26 | INT | output | Maskable interrupt output request to the host processor, in the VIO domain, active low by default. |
| 27 | GPIO_6 | bidirectional | General-purpose I/O in the VRTC domain, with secondary functions NSLEEP, POWERGOOD and REGEN3. |
| 28 | SMPS2_FDBK | input | Output voltage-sense input for SMPS2, or differential negative sense input for SMPS12 in dual-phase configuration; connect to ground if not used. |
| 29 | SMPS2_IN | power_in | Power input for SMPS2, connected to the system supply. |
| 30 | SMPS2_SW | output | Switch node of SMPS2; connect the output inductor. |
| 31 | SMPS1_SW | output | Switch node of SMPS1; connect the output inductor. |
| 32 | SMPS1_IN | power_in | Power input for SMPS1, connected to the system supply. |
| 33 | SMPS1_FDBK | input | Output voltage-sense input for SMPS1, or differential positive sense input for SMPS12 in dual-phase configuration; connect to ground if not used. |
| 34 | VIO_IN | power_in | Digital supply input for GPIOs and I/O supply voltage, 1.8 V (1.71 to 1.89 V) or 3.3 V (3.135 to 3.465 V). |
| 35 | I2C1_SCL_SCK | input | Control I2C serial clock (external pullup) and SPI clock signal, in the VIO domain. |
| 36 | I2C1_SDA_SDI | bidirectional | Control I2C serial bidirectional data (external pullup, open-drain) and SPI input data signal, in the VIO domain. |
| 37 | VCC_SENSE | input | System supply sense line, 3.135 V to VCCA recommended (absolute maximum 7 V). |
| 38 | ADCIN1 | input | GPADC input 1 (absolute maximum 2.4 V); connect to ground if not used. |
| 39 | ADCIN2 | input | GPADC input 2 (absolute maximum 2.4 V); connect to ground if not used. |
| 40 | VBG | output | Bandgap reference voltage output. |
| 41 | REFGND | power_in | System reference ground; connect to ground. |
| 42 | VCCA | power_in | Analog input voltage for internal LDOs and system supply, 3.135 V to 5.25 V recommended (named VSYS). |
| 43 | LDOVANA_OUT | power_out | Internal LDOVANA output voltage. |
| 44 | LDOVRTC_OUT | power_out | Internal LDOVRTC output voltage; connect a pulldown resistor to support rapid power off and on. |
| 45 | NC | unconnected | No connection; leave floating. |
| 46 | SMPS_IN | power_in | Power input for SMPS, connected to the system supply. |
| 47 | NC | unconnected | No connection; leave floating. |
| 48 | SYNCCLKOUT | output | 2.2-MHz fallback switching frequency output for the SMPS, with secondary function 32-kHz digital-gated output clock when VIO_IN is present. |
| 49 | PGND | power_in | Thermal pad (PGND) on the bottom of the package, connected to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management (PMIC) |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
O919A14CTRGZRQ1 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
o919a14ctrgzrq1-etched.step/o919a14ctrgzrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);o919a14ctrgzrq1.step/o919a14ctrgzrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (91 pp, sha256
620c3bdc2d08acc8, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).