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O917A154TRGZRQ1

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Texas Instruments Power Management - Specialized, VQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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O917A154TRGZRQ1

Texas Instruments · Power Management - Specialized · VQFN-48(7x7)

O917A154TRGZRQ1 from Texas Instruments, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO_4 bidirectional General-purpose I/O in the VIO domain (push-pull or open-drain, software PU/PD); secondary functions are REGEN2 output and I2C2_SCL_SCE (DVS I2C clock / SPI chip enable), and it cannot be used as an ON request from OFF mode.
2 GPIO_2 bidirectional General-purpose I/O in the VIO domain (push-pull or open-drain, software PU/PD); secondary functions are ENABLE1 input and I2C2_SDA_SDO (DVS I2C data / SPI data out), and it cannot be used as an ON request from OFF mode.
3 LDO5_IN power_in Power input for LDO5 regulator; recommended range 1.75 V to 5.25 V (3.8 V nominal), absolute maximum 6 V.
4 LDO5_OUT power_out LDO5 output voltage (LDO5 is the low-noise regulator, 100 mA with low-noise operation up to 50 mA).
5 LDO3_IN power_in Power input for LDO3 regulator; recommended range 1.75 V to 5.25 V, absolute maximum 6 V.
6 LDO3_OUT power_out LDO3 output voltage (200 mA regulator).
7 LDO4_OUT power_out LDO4 output voltage (200 mA regulator).
8 LDO4_IN power_in Power input for LDO4 regulator; recommended range 1.75 V to 5.25 V, absolute maximum 6 V.
9 SMPS3_FDBK input Output voltage-sense (feedback) input for SMPS3; absolute maximum 3.6 V and recommended range 0 V to VOUTmax + 0.3 V.
10 SMPS3_IN power_in Power input for SMPS3 from the system supply; recommended range 3.135 V to 5.25 V.
11 SMPS3_SW output Switch node of SMPS3; connect the output inductor here (-2 V to 7 V for 10-ns transients).
12 GPIO_0 bidirectional General-purpose I/O (VRTC fail-safe, 5.25-V tolerant, open-drain output, PPD by default); secondary functions are ENABLE2 input, PWRDOWN input and REGEN1 output.
13 GPIO_1 bidirectional General-purpose I/O (VRTC fail-safe, 5.25-V tolerant, open-drain output, PPD by default); secondary functions are RESET_IN input, NRESWARM input and VBUS_SENSE input.
14 GPIO_3 bidirectional General-purpose I/O (VRTC fail-safe, 5.25-V tolerant, open-drain output, PPD by default); secondary functions are ENABLE2 input, REGEN1 output and SYNCDCDC input.
15 GPIO_5 bidirectional General-purpose I/O (VRTC fail-safe, 5.25-V tolerant, open-drain output, PPD by default); secondary functions are POWERHOLD input and REGEN3 output.
16 BOOT input Tri-level boot pin selecting the power-up sequence; tied to ground or VRTC.
17 SMPS4_FDBK input Output voltage-sense (feedback) input for SMPS4; connect to ground when not used.
18 SMPS4_IN power_in Power input for SMPS4 from the system supply; recommended range 3.135 V to 5.25 V.
19 SMPS4_SW output Switch node of SMPS4; connect the output inductor here (-2 V to 7 V for 10-ns transients).
20 VPROG input OTP programming voltage input (absolute maximum 7 V); ground or float in normal operation, with TESTV as a secondary output function.
21 LDO2_OUT power_out LDO2 output voltage (300 mA regulator with bypass mode).
22 LDO12_IN power_in Common power input for LDO1 and LDO2 regulators from the system supply; LDO1/LDO2 minimum input voltage is not covered by the 1.75 V recommended limit.
23 LDO1_OUT power_out LDO1 output voltage (300 mA regulator with bypass mode).
24 PWRON input External power-on (on-button) input with fixed internal pullup; a low level signals a power-on event.
25 RESET_OUT output System reset or power-on output to the host (low = reset, high = active or sleep); push-pull or open-drain, referenced to VIO.
26 INT output Maskable interrupt output request to the host processor (active low by default), referenced to VIO.
27 GPIO_6 bidirectional General-purpose I/O (VRTC, open-drain output, PPD by default); secondary functions are NSLEEP input, POWERGOOD output and REGEN3 output.
28 SMPS2_FDBK input Negative differential voltage-sense (feedback) input for SMPS2 or for SMPS12 in dual-phase configuration.
29 SMPS2_IN power_in Power input for SMPS2 from the system supply; recommended range 3.135 V to 5.25 V.
30 SMPS2_SW output Switch node of SMPS2; connect the output inductor here (-2 V to 7 V for 10-ns transients).
31 SMPS1_SW output Switch node of SMPS1; connect the output inductor here (-2 V to 7 V for 10-ns transients).
32 SMPS1_IN power_in Power input for SMPS1 from the system supply; recommended range 3.135 V to 5.25 V.
33 SMPS1_FDBK input Output voltage-sense (feedback) input for SMPS1, or positive differential sense input for SMPS12 in dual-phase configuration.
34 VIO_IN power_in Digital supply input for GPIOs and the I/O interfaces; 1.71 V to 1.89 V for 1.8-V I/O or 3.135 V to 3.465 V for 3.3-V I/O.
35 I2C1_SCL_SCK input I2C1 serial clock (external pullup required) or SPI clock input from the host.
36 I2C1_SDA_SDI bidirectional I2C1 serial data (open-drain, external pullup required) or SPI data input from the host.
37 VCC_SENSE input System supply sense input for the VSYS_MON comparator and GPADC channel 3; recommended range 3.135 V to VCCA, absolute maximum 7 V.
38 ADCIN1 input GPADC external input 1; absolute maximum range -0.3 V to 2.4 V.
39 ADCIN2 input GPADC external input 2; absolute maximum range -0.3 V to 2.4 V.
40 VBG output Bandgap reference voltage output of the internal reference.
41 REFGND power_in System reference ground for the device.
42 VCCA power_in Analog input supply for the internal LDOs and system voltage monitoring; recommended range 3.135 V to 5.25 V, absolute maximum 6 V.
43 LDOVANA_OUT power_out Output of the internal LDOVANA regulator.
44 LDOVRTC_OUT power_out Output of the internal LDOVRTC regulator; a pulldown resistor (minimum 3.9 kΩ per the datasheet recommendation) is recommended for fast power-off discharge.
45 SMPS5_FDBK input Output voltage-sense (feedback) input for SMPS5; connect to ground when not used.
46 SMPS5_IN power_in Power input for SMPS5 from the system supply; recommended range 3.135 V to 5.25 V.
47 SMPS5_SW output Switch node of SMPS5; connect the output inductor here (-2 V to 7 V for 10-ns transients).
48 SYNCCLKOUT output Primary function is the 2.2-MHz fallback switching frequency for SMPS; secondary function is a 32-kHz gated output clock when VIO_IN is present.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48(7x7)
Category Power Management (PMIC)
Pins 49

CAD (KiCad official)

  • Symbol: O917A154TRGZRQ1
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: o917a154trgzrq1-etched.step / o917a154trgzrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); o917a154trgzrq1.step / o917a154trgzrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (96 pp, sha256 e2e03bb9c0f75b41, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF