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O917A131TRGZRQ1

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Texas Instruments Power Management - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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O917A131TRGZRQ1

Texas Instruments · Power Management - Specialized · VQFN-48-EP(7x7)

O917A131TRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO_4 bidirectional General-purpose input/output in the VIO domain with secondary functions REGEN2 output and I2C2_SCL_SCE (DVS I2C clock / SPI chip enable); leave floating if unused.
2 GPIO_2 bidirectional General-purpose input/output in the VIO domain with secondary functions ENABLE1 input and I2C2_SDA_SDO (DVS I2C data / SPI output data); leave floating if unused.
3 LDO5_IN power_in Power input voltage for the LDO5 regulator, connected to the system supply.
4 LDO5_OUT power_out LDO5 output voltage; leave floating if unused.
5 LDO3_IN power_in Power input voltage for the LDO3 regulator, connected to the system supply.
6 LDO3_OUT power_out LDO3 output voltage; leave floating if unused.
7 LDO4_OUT power_out LDO4 output voltage; leave floating if unused.
8 LDO4_IN power_in Power input voltage for the LDO4 regulator, connected to the system supply.
9 SMPS3_FDBK input Output voltage-sense (feedback) input for SMPS3; leave floating if unused.
10 SMPS3_IN power_in Power input for SMPS3, connected to the system supply.
11 SMPS3_SW output Switch node of SMPS3; connect the output inductor, leave floating if unused.
12 GPIO_0 bidirectional VRTC-domain fail-safe (5.25-V tolerant) general-purpose I/O with secondary functions ENABLE2, PWRDOWN inputs and REGEN1 output.
13 GPIO_1 bidirectional VRTC-domain fail-safe (5.25-V tolerant) general-purpose I/O with secondary inputs RESET_IN, VBUS_SENSE and NRESWARM.
14 GPIO_3 bidirectional VRTC-domain fail-safe (5.25-V tolerant) general-purpose I/O with secondary functions REGEN1 output, ENABLE2 input and SYNCDCDC (SMPS clock synchronization) input.
15 GPIO_5 bidirectional VRTC-domain fail-safe (5.25-V tolerant) general-purpose I/O with secondary functions POWERHOLD input and REGEN3 output.
16 BOOT input Boot ball for power-up sequence selection (tri-level input, VRTC level); connect to ground or VRTC if unused.
17 SMPS4_FDBK input Output voltage-sense (feedback) input for SMPS4; connect to ground if unused.
18 SMPS4_IN power_in Power input for SMPS4, connected to the system supply.
19 SMPS4_SW output Switch node of SMPS4; connect the output inductor, leave floating if unused.
20 VPROG bidirectional OTP programming voltage input (primary function, absolute maximum 7 V) and TESTV output (secondary function); connect to ground or leave floating.
21 LDO2_OUT power_out LDO2 output voltage; leave floating if unused.
22 LDO12_IN power_in Power input voltage for the LDO1 and LDO2 regulators, connected to the system supply.
23 LDO1_OUT power_out LDO1 output voltage; leave floating if unused.
24 PWRON input External power-on event (on-button switch-on) input with fixed pullup at VSYS (VCCA) level, active low; leave floating if unused.
25 RESET_OUT output System reset or power-on output in the VIO domain (low = reset, high = active or sleep); leave floating if unused.
26 INT output Maskable interrupt output request to the host processor in the VIO domain, active low by default.
27 GPIO_6 bidirectional VRTC-domain general-purpose I/O with secondary functions NSLEEP input, POWERGOOD output and REGEN3 output.
28 SMPS2_FDBK input Output voltage-sense (feedback) input for SMPS2, or differential negative sense input for SMPS12 in dual-phase configuration; connect to ground if unused.
29 SMPS2_IN power_in Power input for SMPS2, connected to the system supply.
30 SMPS2_SW output Switch node of SMPS2; connect the output inductor, leave floating if unused.
31 SMPS1_SW output Switch node of SMPS1; connect the output inductor, leave floating if unused.
32 SMPS1_IN power_in Power input for SMPS1, connected to the system supply.
33 SMPS1_FDBK input Output voltage-sense (feedback) input for SMPS1, or differential positive sense input for SMPS12 in dual-phase configuration; connect to ground if unused.
34 VIO_IN power_in Digital supply input for GPIOs and I/O supply voltage, 1.71 to 1.89 V (1.8 V) or 3.135 to 3.465 V (3.3 V).
35 I2C1_SCL_SCK input Control I2C serial clock (external pullup) and SPI clock signal, VIO domain.
36 I2C1_SDA_SDI bidirectional Control I2C serial bidirectional data (external pullup) and SPI input data signal, VIO domain.
37 VCC_SENSE input System supply sense line, 3.135 V to VCCA (VCCA - 1 V when HIGH_VCC_SENSE = 1), absolute maximum 7 V.
38 ADCIN1 input GPADC input 1, absolute maximum 2.4 V; connect to ground if unused.
39 ADCIN2 input GPADC input 2, absolute maximum 2.4 V; connect to ground if unused.
40 VBG output Bandgap reference voltage output.
41 REFGND power_in System reference ground; connect to ground.
42 VCCA power_in Analog input voltage for internal LDOs and system supply input, 3.135 to 5.25 V recommended, absolute maximum 6 V.
43 LDOVANA_OUT power_out Internal LDOVANA regulator output voltage.
44 LDOVRTC_OUT power_out Internal LDOVRTC regulator output voltage; connect a pulldown resistor (minimum 3.9 kΩ) to support rapid power off and on.
45 SMPS5_FDBK input Output voltage-sense (feedback) input for SMPS5; connect to ground if unused.
46 SMPS5_IN power_in Power input for SMPS5, connected to the system supply.
47 SMPS5_SW output Switch node of SMPS5; connect the output inductor, leave floating if unused.
48 SYNCCLKOUT output 2.2-MHz fallback switching frequency output for SMPS (primary) or 32-kHz gated output clock when VIO_IN is present (secondary); leave floating if unused.
49 PGND power_in Thermal pad, labeled PGND, connected to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Power Management (PMIC)
Pins 49

CAD (KiCad official)

  • Symbol: O917A131TRGZRQ1
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: o917a131trgzrq1-etched.step / o917a131trgzrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); o917a131trgzrq1.step / o917a131trgzrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (96 pp, sha256 e2e03bb9c0f75b41, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF